[PATCH 3/3] rtc: pcf2127: Disable the 100th counter for PCF2131

[Herve Codina <herve.codina@bootlin.com>]

The PCF2131 has a 100th counter. This counter is enabled by default but
100th seconds values are not used in the RTC subsystem.

In order to save energy when the PCF2131 is powered by its battery,
disable this counter.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 drivers/rtc/rtc-pcf2127.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 1bb84f72cf5f..d090e7d063c4 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -35,6 +35,7 @@
 #define PCF2127_REG_CTRL1		0x00
 #define PCF2127_BIT_CTRL1_POR_OVRD		BIT(3)
 #define PCF2127_BIT_CTRL1_TSF1			BIT(4)
+#define PCF2131_BIT_CTRL1_100TH_S_DIS		BIT(4) /* Replace PCF2127 TSF1 bit */
 #define PCF2127_BIT_CTRL1_STOP			BIT(5)
 /* Control register 2 */
 #define PCF2127_REG_CTRL2		0x01
@@ -1455,6 +1456,20 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
 		ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
 	}
 
+	/*
+	 * PCF2131 has a 100th seconds counter enabled by default. 100th seconds
+	 * are not used.
+	 *
+	 * In order to save energy when the RTC is powered by its battery, fully
+	 * disable this counter.
+	 */
+	if (pcf2127->cfg->type == PCF2131) {
+		ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+				      PCF2131_BIT_CTRL1_100TH_S_DIS);
+		if (ret < 0)
+			return ret;
+	}
+
 	/*
 	 * The "Power-On Reset Override" facility prevents the RTC to do a reset
 	 * after power on. For normal operation the PORO must be disabled.
-- 
2.56.0