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Mon, 02 Nov 2026 09:45:11 -0800 (PST) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a42935b4asm53290803eec.16.2026.11.02.09.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 09:45:11 -0800 (PST) From: Coia Prant To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Frank Wunderlich , Peter Geis , Junhao Xie , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v3 3/6] arm64: dts: rockchip: fix GMAC clock setup on BPI-R2 Pro Date: Tue, 3 Nov 2026 01:44:47 +0800 Message-ID: <20261102174450.3000397-4-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261102174450.3000397-1-coiaprant@gmail.com> References: <20261102174450.3000397-1-coiaprant@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Both GMAC nodes rely on the internal 125 MHz GMAC main clock, but neither pins its rate explicitly. Add assigned-clock-rates = <0>, <125000000> so SCLK_GMACx is fixed at 125 MHz instead of whatever the bootloader or the hardware reset left. The RGMII speed clock (SCLK_GMACx_RX_TX) stays at 0, since it is managed at runtime by rk_set_clk_tx_rate(). For gmac0, also switch clock_in_out from "input" to "output". The port uses a fixed-link, and there is no external 125 MHz clock feeding the MAC, so "input" described a clock source that is not wired up. Note that on RK3568 clock_in_out does not change the hardware clock routing today (rk3568_ops has no io_clksel masks), so this corrects the description rather than the behaviour. Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") Signed-off-by: Coia Prant --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 4d3ebe50b90ba..677b6261a3a1e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -206,7 +206,8 @@ &combphy2 { &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - clock_in_out = "input"; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim @@ -232,6 +233,7 @@ fixed-link { &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii"; -- 2.47.3