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Tue, 03 Nov 2026 05:51:30 -0800 (PST) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1ac13ef1d4dsm39536340c88.3.2026.11.03.05.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 05:51:29 -0800 (PST) From: joonhoekim <26rote@gmail.com> To: sashiko-reviews@lists.linux.dev Cc: Joonhoe Kim <26rote@gmail.com>, sashiko-bot@kernel.org, Thinh Nguyen , Greg Kroah-Hartman , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-usb@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/3] usb: dwc3: qcom: Use the UTMI clock as PIPE clock in DisplayPort-only modes Date: Tue, 3 Nov 2026 22:51:29 +0900 Message-ID: <20261103135129.1961-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 In-Reply-To: References: <20261102215121.738-1-26rote@gmail.com> <20261102215121.738-3-26rote@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Joonhoe Kim <26rote@gmail.com> On Mon, 02 Nov 2026 22:08:43 +0000, sashiko-bot@kernel.org wrote: > [Severity: High] > Can the controller get stuck on the UTMI clock after leaving a > DisplayPort-only mode? [...] > 1. dwc3_qcom_set_role_notifier(USB_ROLE_HOST) runs while qcom->dp_only is > still true, so dwc3_qcom_update_pipe_clk() does nothing and > qcom->current_role becomes USB_ROLE_HOST. > 2. dwc3_qcom_mux_set() runs next and sets qcom->dp_only = false (for > TYPEC_STATE_USB or TYPEC_DP_STATE_D), then returns early because > !qcom->dp_only is true. This is partly right. The replug case is a real gap. On the Lenovo Y700 Gen 5 (TB323FU, Kaanapali), the USB mux state has always arrived before the role change. But nothing guarantees that order. In v2, dwc3_qcom_mux_set() switches back to the PIPE clock itself. It does so when a USB state arrives after the safe state. Once DisplayPort is powered off, the PHY leaves DP-only mode in the same typec_mux_set() call. So the switch no longer waits for a role change. If DisplayPort is still powered then, the PHY delays the switch but the controller does not. v2 does not cover that case. The other cases do not leave the controller behind the PHY. qmp_combo_typec_mux_set() does not leave DP-only mode while the DP PHY is powered ("DP PHY is still in use, delaying switch"). This covers an in-place change from C/E to D/F. It also covers a USB state without a safe state before it. In both cases the PIPE clock stays stopped, so the UTMI clock is the right choice. Your question made me find the opposite problem, though. After an in-place change from C/E to D/F, this version clears dp_only. The next role change then selects the PIPE clock while the PHY is still in DP-only mode. v2 keeps dp_only unchanged while DisplayPort is active, as the PHY does. > [Severity: High] > What happens here when CONFIG_USB_DWC3_QCOM=y and CONFIG_TYPEC=m, or when > CONFIG_TYPEC=n? Right, thanks. The arm64 defconfig has exactly USB_DWC3_QCOM=y and TYPEC=m, so the vmlinux link fails. With TYPEC=n, the stub returns -EOPNOTSUPP and the probe fails. v2 adds "depends on TYPEC || TYPEC=n" to USB_DWC3_QCOM, as PHY_QCOM_QMP_COMBO has. It also skips the mux registration when CONFIG_TYPEC is disabled. With this dependency, the arm64 defconfig builds the glue as a module. If that is not wanted, the mux part could go behind its own Kconfig option instead. v2: https://lore.kernel.org/all/20261103135057.1682-1-26rote@gmail.com/ Thanks, Joonhoe Kim