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[93.34.90.148]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48fc9d6b0aasm417802f8f.2.2026.11.03.11.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 11:50:22 -0800 (PST) From: Christian Marangi To: Christian Marangi , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY Date: Tue, 3 Nov 2026 20:49:59 +0100 Message-ID: <20261103195007.9721-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261103195007.9721-1-ansuelsmth@gmail.com> References: <20261103195007.9721-1-ansuelsmth@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port work. Add the required register to configure the PCIe PHY and provide an example for it. The PHY link to another PHY (the QPHY as described in the YAML) to correctly handle Gen2 speed and mode. It's mandatory to have this PHY configured for correct functionality of PCIe. The QPHY is a unified PHY that both handle USB and PCIe PHY. It's also mondatory that the QPHY setup is done in the PCIe PHY setup and calibration phase or calibration might fail. Signed-off-by: Christian Marangi --- .../phy/airoha,an7583-pcie-gen3-phy.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml new file mode 100644 index 000000000000..a8ec5ac781cc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-gen3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 PCI-Express PHY + +maintainers: + - Christian Marangi + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. + +properties: + compatible: + const: airoha,an7583-pcie-gen3-phy + + reg: + items: + - description: PCIE G3 analog base address + - description: PCIE G3 PMA base address + - description: PCIE detection time base address + - description: PCIE Rx AEQ base address + + reg-names: + items: + - const: g3-ana + - const: g3-pma + - const: xr-dtime + - const: rx-aeq + + phys: + items: + - description: phandle to QPHY phy for Gen2 support + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - phys + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + phy@1fc7f000 { + compatible = "airoha,an7583-pcie-gen3-phy"; + reg = <0x1fc7f000 0x1000>, + <0x1fc7e000 0x1000>, + <0x1fc30044 0x4>, + <0x1fc35030 0x4>; + reg-names = "g3-ana", "g3-pma", + "xr-dtime", "rx-aeq"; + + phys = <&pcie1_phy PHY_TYPE_PCIE>; + + #phy-cells = <0>; + }; -- 2.55.0