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Wed, 04 Nov 2026 08:47:15 -0800 (PST) Received: from Sobhana.localdomain ([157.51.207.207]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c57430sm10839666c88.18.2026.11.04.08.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 08:47:15 -0800 (PST) From: Sreeshankar K Date: Wed, 04 Nov 2026 16:46:35 +0000 Subject: [PATCH v13 3/8] thermal/drivers/qcom/lmh: Switch to match data for SoC CPU-to-node mappings X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-master-v13-3-355b65c6f764@gmail.com> References: <20261104-master-v13-0-355b65c6f764@gmail.com> In-Reply-To: <20261104-master-v13-0-355b65c6f764@gmail.com> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Konrad Dybcio , Robert Marko , Guru Das Srinagesh , Viresh Kumar , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793810796; l=4488; i=sreeshankar0910@gmail.com; s=20261029; h=from:subject:message-id; bh=VU3SQSKgFReF5BiO2cKpUAobqELNHDdICbyBD7TlHBc=; b=zEQCRQG3leyhQotPeA5MCZh/7vfckyMF2IzU+0IxPHpx8ud6vbLpA0+Et2DgDiTWDZbxXhkrL j/JgrQU0zoCDYa1IoTh9tAQDpIItm9Dg7NXu4XbjUYF5XSuUW4NhvDj X-Developer-Key: i=sreeshankar0910@gmail.com; a=ed25519; pk=CGSHduvtn2hwLCNRXRc9s/fh6X8PH/zNdp08zC8hOuQ= lmh_probe() hardcodes the mapping of logical CPU IDs to LMh hardware cluster node IDs: CPU 0 maps to LMH_CLUSTER0_NODE_ID, and CPU 4 maps to LMH_CLUSTER1_NODE_ID. This assumption only holds true for 4+4 big.LITTLE architectures like SDM845 and SM8150. On platforms with asymmetric cluster layouts, such as the 6+2 topology on SM7250 where the big cluster starts at logical CPU 6, lmh_probe() fails with -EINVAL. Consequently, the second LMh node does not register its interrupt domain, which in turn causes dependent drivers like qcom-cpufreq-hw to fail or indefinitely defer probing via fw_devlink. Address this by introducing a SoC descriptor structure (struct qcom_lmh_soc_data) and an explicit mapping table (struct qcom_lmh_node_map) associated with of_device_id match data. This encapsulates both the algorithm enable flags and the CPU-to-node mappings per compatible string. Signed-off-by: Sreeshankar K --- drivers/thermal/qcom/lmh.c | 73 +++++++++++++++++++++++++++++++++------------- 1 file changed, 53 insertions(+), 20 deletions(-) diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c index 99396b93e..ef49ed1c6 100644 --- a/drivers/thermal/qcom/lmh.c +++ b/drivers/thermal/qcom/lmh.c @@ -94,19 +94,61 @@ static const struct irq_domain_ops lmh_irq_ops = { .xlate = irq_domain_xlate_onecell, }; +struct qcom_lmh_node_map { + int cpu_id; + u32 node_id; +}; + +struct qcom_lmh_soc_data { + uintptr_t flags; + const struct qcom_lmh_node_map *map; + size_t num_nodes; +}; + +static const struct qcom_lmh_node_map sdm845_lmh_map[] = { + { .cpu_id = 0, .node_id = LMH_CLUSTER0_NODE_ID }, + { .cpu_id = 4, .node_id = LMH_CLUSTER1_NODE_ID }, +}; + +static const struct qcom_lmh_soc_data sdm845_lmh_data = { + .map = sdm845_lmh_map, + .num_nodes = ARRAY_SIZE(sdm845_lmh_map), + .flags = LMH_ENABLE_ALGOS, +}; + +static const struct qcom_lmh_soc_data sm8150_lmh_data = { + .map = sdm845_lmh_map, + .num_nodes = ARRAY_SIZE(sdm845_lmh_map), +}; + +static const struct of_device_id lmh_table[] = { + { .compatible = "qcom,sc8180x-lmh", .data = &sm8150_lmh_data }, + { .compatible = "qcom,sdm845-lmh", .data = &sdm845_lmh_data }, + { .compatible = "qcom,sm8150-lmh", .data = &sm8150_lmh_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lmh_table); + static int lmh_probe(struct platform_device *pdev) { + const struct qcom_lmh_soc_data *soc_data; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct device_node *cpu_node; struct lmh_hw_data *lmh_data; int temp_low, temp_high, temp_arm, cpu_id, ret; unsigned int enable_alg; + bool found = false; u32 node_id; + int i; if (!qcom_scm_is_available()) return -EPROBE_DEFER; + soc_data = of_device_get_match_data(dev); + if (!soc_data) + return -EINVAL; + lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL); if (!lmh_data) return -ENOMEM; @@ -139,24 +181,23 @@ static int lmh_probe(struct platform_device *pdev) return ret; } - /* - * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed - * for other platforms, revisit this to check if the should be part - * of a dt match table. - */ - if (cpu_id == 0) { - node_id = LMH_CLUSTER0_NODE_ID; - } else if (cpu_id == 4) { - node_id = LMH_CLUSTER1_NODE_ID; - } else { - dev_err(dev, "Wrong CPU id associated with LMh node\n"); + for (i = 0; i < soc_data->num_nodes; i++) { + if (cpu_id == soc_data->map[i].cpu_id) { + node_id = soc_data->map[i].node_id; + found = true; + break; + } + } + + if (!found) { + dev_err(dev, "Wrong CPU id %d associated with LMh node\n", cpu_id); return -EINVAL; } if (!qcom_scm_lmh_dcvsh_available()) return -EINVAL; - enable_alg = (uintptr_t)of_device_get_match_data(dev); + enable_alg = soc_data->flags; if (enable_alg) { ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1, @@ -230,14 +271,6 @@ static int lmh_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id lmh_table[] = { - { .compatible = "qcom,sc8180x-lmh", }, - { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS}, - { .compatible = "qcom,sm8150-lmh", }, - {} -}; -MODULE_DEVICE_TABLE(of, lmh_table); - static struct platform_driver lmh_driver = { .probe = lmh_probe, .driver = { -- 2.43.0