From: Sheetal <sheetal@nvidia.com>
To: Vinod Koul <vkoul@kernel.org>, Rob Herring <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Frank Li <Frank.Li@kernel.org>,
Laxman Dewangan <ldewangan@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@kernel.org>,
Mohan Kumar <mkumard@nvidia.com>,
Sameer Pujar <spujar@nvidia.com>, <dmaengine@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, Sheetal <sheetal@nvidia.com>
Subject: [PATCH 0/3] dmaengine: tegra210-adma: Add Tegra268 support
Date: Wed, 4 Nov 2026 11:09:29 +0000 [thread overview]
Message-ID: <20261104110932.1097294-1-sheetal@nvidia.com> (raw)
Tegra268 reuses the Tegra264 ADMA register layout but has ten DMA
channels, five request IDs, six pages and a different uniform FIFO size.
Add its binding and SoC data, and derive the shared page configuration
masks from these limits.
Make the Tegra264 FIFO size explicit first so Tegra268 can select its
FIFO size without changing the existing devices' FIFO programming.
Anupama Kunkulagunta (2):
dt-bindings: dma: nvidia,tegra210-adma: Add Tegra268 support
dmaengine: tegra210-adma: Add Tegra268 support
Sheetal (1):
dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit
.../bindings/dma/nvidia,tegra210-adma.yaml | 13 ++++
drivers/dma/tegra210-adma.c | 73 +++++++++++++++----
2 files changed, 73 insertions(+), 13 deletions(-)
--
2.43.0
next reply other threads:[~2026-11-04 11:10 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 11:09 Sheetal [this message]
2026-11-04 11:09 ` [PATCH 1/3] dt-bindings: dma: nvidia,tegra210-adma: Add Tegra268 support Sheetal
2026-11-04 11:09 ` [PATCH 2/3] dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit Sheetal
2026-11-04 11:09 ` [PATCH 3/3] dmaengine: tegra210-adma: Add Tegra268 support Sheetal
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