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Wed, 4 Nov 2026 03:10:02 -0800 Received: from build-sheetal-noble-20261014.internal (10.127.8.14) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Wed, 4 Nov 2026 03:10:02 -0800 From: Sheetal To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Frank Li , Laxman Dewangan , Jonathan Hunter , Thierry Reding , Mohan Kumar , Sameer Pujar , , , , , Sheetal Subject: [PATCH 2/3] dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit Date: Wed, 4 Nov 2026 11:09:31 +0000 Message-ID: <20261104110932.1097294-3-sheetal@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261104110932.1097294-1-sheetal@nvidia.com> References: <20261104110932.1097294-1-sheetal@nvidia.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH3PEPF0005961B:EE_|DM6PR12MB4433:EE_ X-MS-Office365-Filtering-Correlation-Id: 06388c55-6a2d-4a9b-34e2-08df3a643659 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|23010399003|376014|7416014|1800799024|10067099003|18002099003|22082099003|56012099006|11063799006|261022105027099003|261026140227099003|261102123227099003|261028144727099003|261009223027099003|261021123027099003|261021121427099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lTqg1emMTSE5vdJPKuOjd8WAVh2jdGeVr5ptURyFFIU0zlKdV0IrUR3axHX3Ibg6naql/Z+eMewlmxuUX9uY/NxjASl0L43cgyXO2ChiYoV8/ge8dgP0IAVS7BXzmsTXNLwbJ+nRPwNcMvUqTzTXbXhvZZXrZ0KkK45EIBnFprNxOeRw81NhZLiv39nyKXErZhPq+5u0SO9dqw8fzRjyzvetUSn+zaCxBfhlYCsTmf0pdhvPz2fbr4qMf5m2kwpIYtPHN/zzu/C9+ad0gxC6PLh88L28UTCAaZyrRIo2AeRqY4T31Z4TzQGWS0a4DHU2wKO8Cr9gAd2oH7/oqJOj/cbRpkx9HqRETDSIF6lDQtfbxJrJumfs+TCXZOilBbIQ6RL/ctexw/sCcAUREqZUKLk5CClusJqP55HcpPCc0JUVV/KZWI7IAbCbdmHz/PeB X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 11:10:19.1870 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06388c55-6a2d-4a9b-34e2-08df3a643659 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: PH3PEPF0005961B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4433 Tegra264 uses the same ADMA FIFO size for every ADMAIF request. The driver currently obtains this by setting sreq_index_offset to zero, which makes every valid request select a FIFO size of 2. Add a SoC data field for the uniform FIFO size and set it to 2 for Tegra264. Retain the request-index-based FIFO selection for earlier SoCs. This preserves existing FIFO programming and allows devices with a different uniform FIFO size to specify it in their SoC data. Signed-off-by: Sheetal --- drivers/dma/tegra210-adma.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 21a381d022cf..293a1119e07a 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -101,6 +101,7 @@ struct tegra_adma; * @ch_reg_size: Size of DMA channel register space. * @nr_channels: Number of DMA channels available. * @ch_fifo_size_mask: Mask for FIFO size field. + * @ch_fifo_size: FIFO size for devices with uniform channel FIFO size. * @sreq_index_offset: Slave channel index offset. * @max_page: Maximum ADMA Channel Page. * @set_global_pg_config: Global page programming. @@ -125,6 +126,7 @@ struct tegra_adma_chip_data { unsigned int ch_reg_size; unsigned int nr_channels; unsigned int ch_fifo_size_mask; + unsigned int ch_fifo_size; unsigned int sreq_index_offset; unsigned int max_page; void (*set_global_pg_config)(struct tegra_adma *tdma); @@ -725,18 +727,28 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, * * ADMA FIFO size is set as per below (based on default ADMAIF channel * FIFO sizes): + * For Tegra264: + * fifo_size = ch_fifo_size + * For devices prior to Tegra264: * fifo_size = 0x2 (sreq_index > sreq_index_offset) * fifo_size = 0x3 (sreq_index <= sreq_index_offset) * */ - if (tdc->sreq_index > cdata->sreq_index_offset) + if (cdata->ch_fifo_size) { ch_regs->fifo_ctrl = - ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask, - fifo_size_shift); - else - ch_regs->fifo_ctrl = - ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask, + ADMA_CH_REG_FIELD_VAL(cdata->ch_fifo_size, + cdata->ch_fifo_size_mask, fifo_size_shift); + } else { + if (tdc->sreq_index > cdata->sreq_index_offset) + ch_regs->fifo_ctrl = + ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask, + fifo_size_shift); + else + ch_regs->fifo_ctrl = + ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask, + fifo_size_shift); + } ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; @@ -1018,7 +1030,7 @@ static const struct tegra_adma_chip_data tegra264_chip_data = { .ch_reg_size = 0x100, .nr_channels = 64, .ch_fifo_size_mask = 0x7f, - .sreq_index_offset = 0, + .ch_fifo_size = 2, .max_page = 10, .set_global_pg_config = tegra264_adma_global_page_config, }; -- 2.43.0