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Wed, 4 Nov 2026 03:19:00 -0800 Received: from build-sheetal-noble-20261014.internal (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Wed, 4 Nov 2026 03:18:59 -0800 From: Sheetal To: Liam Girdwood , Mark Brown , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" CC: Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan Kumar , Sameer Pujar , , , , , "Anupama Kunkulagunta" , Sheetal Subject: [PATCH 2/2] ASoC: tegra: ADMAIF: Add Tegra268 support Date: Wed, 4 Nov 2026 11:18:36 +0000 Message-ID: <20261104111836.1100527-3-sheetal@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261104111836.1100527-1-sheetal@nvidia.com> References: <20261104111836.1100527-1-sheetal@nvidia.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN5PEPF0004698A:EE_|SA1PR12MB6869:EE_ X-MS-Office365-Filtering-Correlation-Id: b890e3a9-988c-4f9a-ed0f-08df3a657545 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|7416014|376014|82310400026|1800799024|10067099003|261022105027099003|261021121427099003|261022075727099003|261009223027099003|11063799006|261028144727099003|261026140227099003|56012099006|18002099003|22082099003|261102123227099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UjdwVCvrzmMddvoZ1dtmXCUPte/1NMbSCoZoFTFUpG1P16eZkeZHv5SlVfzFmA4o0R0llq+X253GmM9IxTw2vDSpH/X9rP7VyocIaTNxTZqq/LUltEqVRJIdzfW9GgBZEBonsmOaQNHeo1UZFaVvt8Mf2eSaeBScUEHkcBGg8d5EyYcj89GFVWhdX7kB8pfnvvWqsyNQy64CVMf4Bs3fiNOis36+wwCRDKDBJQPaHs4slVUBojW8RGUSrieNK47GavXtjxEb+uKhDAPzg5l27g+zg3C7nO/QpuwiJeH4qbz6CsddOP2XV0I6mafVrNPifFdkzGZHP8Df9XDFz0zkeB+5ysyRw4rMtdENLZ2UQPeCu5CR6jrpPOjxzpTD83YK4ahPYU7addFTjvfi/gKfe+HwjHu0JX7wu9PpKs9f1zBnMziHUedCmIVdapYXq9od X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 11:19:14.1811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b890e3a9-988c-4f9a-ed0f-08df3a657545 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN5PEPF0004698A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6869 From: Anupama Kunkulagunta Tegra268 reuses the Tegra264 ADMAIF register layout but provides only five RX and five TX interfaces. Add the compatible and SoC data for this configuration. Add register defaults and five-entry DAI and control tables. Retain the Tegra264 32-channel per-stream limit and use Tegra268 FIFO defaults. Set the register bound one stride past the final global TX enable status register so the access callbacks mark it readable and volatile. Signed-off-by: Anupama Kunkulagunta Signed-off-by: Sheetal --- sound/soc/tegra/tegra210_admaif.c | 66 +++++++++++++++++++++++++++++++ sound/soc/tegra/tegra210_admaif.h | 20 ++++++++++ 2 files changed, 86 insertions(+) diff --git a/sound/soc/tegra/tegra210_admaif.c b/sound/soc/tegra/tegra210_admaif.c index 87e898cc35e4..72a245ced209 100644 --- a/sound/soc/tegra/tegra210_admaif.c +++ b/sound/soc/tegra/tegra210_admaif.c @@ -184,6 +184,20 @@ static const struct reg_default tegra264_admaif_reg_defaults[] = { {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003} }; +static const struct reg_default tegra268_admaif_reg_defaults[] = { + ADMAIF_RX_REG_DEFAULTS(1, TEGRA268), + ADMAIF_RX_REG_DEFAULTS(2, TEGRA268), + ADMAIF_RX_REG_DEFAULTS(3, TEGRA268), + ADMAIF_RX_REG_DEFAULTS(4, TEGRA268), + ADMAIF_RX_REG_DEFAULTS(5, TEGRA268), + ADMAIF_TX_REG_DEFAULTS(1, TEGRA268), + ADMAIF_TX_REG_DEFAULTS(2, TEGRA268), + ADMAIF_TX_REG_DEFAULTS(3, TEGRA268), + ADMAIF_TX_REG_DEFAULTS(4, TEGRA268), + ADMAIF_TX_REG_DEFAULTS(5, TEGRA268), + {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA268_ADMAIF_GLOBAL_BASE), 0x00000003} +}; + static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg) { struct tegra_admaif *admaif = dev_get_drvdata(dev); @@ -342,6 +356,20 @@ static const struct regmap_config tegra264_admaif_regmap_config = { .cache_type = REGCACHE_FLAT, }; +static const struct regmap_config tegra268_admaif_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = TEGRA268_ADMAIF_LAST_REG, + .writeable_reg = tegra_admaif_wr_reg, + .readable_reg = tegra_admaif_rd_reg, + .volatile_reg = tegra_admaif_volatile_reg, + .reg_defaults = tegra268_admaif_reg_defaults, + .num_reg_defaults = TEGRA268_ADMAIF_CHANNEL_COUNT * 6 + 1, + .reg_default_cb = regmap_default_zero_cb, + .cache_type = REGCACHE_FLAT, +}; + static int tegra_admaif_runtime_suspend(struct device *dev) { struct tegra_admaif *admaif = dev_get_drvdata(dev); @@ -796,6 +824,14 @@ static struct snd_soc_dai_driver tegra264_admaif_cmpnt_dais[] = { DAI("ADMAIF32", TEGRA264_ADMAIF_MAX_CHANNEL), }; +static struct snd_soc_dai_driver tegra268_admaif_cmpnt_dais[] = { + DAI("ADMAIF1", TEGRA268_ADMAIF_MAX_CHANNEL), + DAI("ADMAIF2", TEGRA268_ADMAIF_MAX_CHANNEL), + DAI("ADMAIF3", TEGRA268_ADMAIF_MAX_CHANNEL), + DAI("ADMAIF4", TEGRA268_ADMAIF_MAX_CHANNEL), + DAI("ADMAIF5", TEGRA268_ADMAIF_MAX_CHANNEL), +}; + static const char * const tegra_admaif_stereo_conv_text[] = { "CH0", "CH1", "AVG", }; @@ -908,6 +944,14 @@ static struct snd_kcontrol_new tegra264_admaif_controls[] = { TEGRA_ADMAIF_CIF_CTRL(32), }; +static struct snd_kcontrol_new tegra268_admaif_controls[] = { + TEGRA_ADMAIF_CIF_CTRL(1), + TEGRA_ADMAIF_CIF_CTRL(2), + TEGRA_ADMAIF_CIF_CTRL(3), + TEGRA_ADMAIF_CIF_CTRL(4), + TEGRA_ADMAIF_CIF_CTRL(5), +}; + static const struct snd_soc_component_driver tegra210_admaif_cmpnt = { .controls = tegra210_admaif_controls, .num_controls = ARRAY_SIZE(tegra210_admaif_controls), @@ -938,6 +982,16 @@ static const struct snd_soc_component_driver tegra264_admaif_cmpnt = { .pointer = tegra_pcm_pointer, }; +static const struct snd_soc_component_driver tegra268_admaif_cmpnt = { + .controls = tegra268_admaif_controls, + .num_controls = ARRAY_SIZE(tegra268_admaif_controls), + .pcm_new = tegra_pcm_new, + .open = tegra_pcm_open, + .close = tegra_pcm_close, + .hw_params = tegra_pcm_hw_params, + .pointer = tegra_pcm_pointer, +}; + static const struct tegra_admaif_soc_data soc_data_tegra210 = { .num_ch = TEGRA210_ADMAIF_CHANNEL_COUNT, .max_stream_ch = TEGRA210_ADMAIF_MAX_CHANNEL, @@ -971,10 +1025,22 @@ static const struct tegra_admaif_soc_data soc_data_tegra264 = { .rx_base = TEGRA264_ADMAIF_RX_BASE, }; +static const struct tegra_admaif_soc_data soc_data_tegra268 = { + .num_ch = TEGRA268_ADMAIF_CHANNEL_COUNT, + .max_stream_ch = TEGRA268_ADMAIF_MAX_CHANNEL, + .cmpnt = &tegra268_admaif_cmpnt, + .dais = tegra268_admaif_cmpnt_dais, + .regmap_conf = &tegra268_admaif_regmap_config, + .global_base = TEGRA268_ADMAIF_GLOBAL_BASE, + .tx_base = TEGRA268_ADMAIF_TX_BASE, + .rx_base = TEGRA268_ADMAIF_RX_BASE, +}; + static const struct of_device_id tegra_admaif_of_match[] = { { .compatible = "nvidia,tegra210-admaif", .data = &soc_data_tegra210 }, { .compatible = "nvidia,tegra186-admaif", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra264-admaif", .data = &soc_data_tegra264 }, + { .compatible = "nvidia,tegra268-admaif", .data = &soc_data_tegra268 }, {}, }; MODULE_DEVICE_TABLE(of, tegra_admaif_of_match); diff --git a/sound/soc/tegra/tegra210_admaif.h b/sound/soc/tegra/tegra210_admaif.h index fd9877aa95d3..4a7fff91f8bb 100644 --- a/sound/soc/tegra/tegra210_admaif.h +++ b/sound/soc/tegra/tegra210_admaif.h @@ -31,6 +31,14 @@ #define TEGRA264_ADMAIF_TX_BASE 0x1000 #define TEGRA264_ADMAIF_GLOBAL_BASE 0x2000 #define TEGRA264_ADMAIF_MAX_CHANNEL 32 +/* Tegra268 specific */ +#define TEGRA268_ADMAIF_CHANNEL_COUNT 5 +#define TEGRA268_ADMAIF_RX_BASE TEGRA264_ADMAIF_RX_BASE +#define TEGRA268_ADMAIF_TX_BASE TEGRA264_ADMAIF_TX_BASE +#define TEGRA268_ADMAIF_GLOBAL_BASE TEGRA264_ADMAIF_GLOBAL_BASE +#define TEGRA268_ADMAIF_LAST_REG (TEGRA268_ADMAIF_GLOBAL_BASE + \ + TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS + 4) +#define TEGRA268_ADMAIF_MAX_CHANNEL TEGRA264_ADMAIF_MAX_CHANNEL /* Global registers */ #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0 #define TEGRA_ADMAIF_GLOBAL_CG_0 0x8 @@ -204,6 +212,18 @@ #define TEGRA264_ADMAIF_TX30_FIFO_CTRL_REG_DEFAULT 0x01800257 #define TEGRA264_ADMAIF_TX31_FIFO_CTRL_REG_DEFAULT 0x0180025a #define TEGRA264_ADMAIF_TX32_FIFO_CTRL_REG_DEFAULT 0x0180025d +/* Default values - Tegra268 */ +#define TEGRA268_ADMAIF_CIF_REG_DEFAULT 0x00003f00 +#define TEGRA268_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000500 +#define TEGRA268_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000507 +#define TEGRA268_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x0000050e +#define TEGRA268_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x00000514 +#define TEGRA268_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000051a +#define TEGRA268_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x03000500 +#define TEGRA268_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x03000507 +#define TEGRA268_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x0300050e +#define TEGRA268_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x03000514 +#define TEGRA268_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0300051a enum { DATA_8BIT, -- 2.43.0