From: Vladimir Zapolskiy <vz@kernel.org>
To: Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Abel Vesa <abelvesa@kernel.org>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH 4/4] arm64: dts: qcom: sm8350: Add CAMSS device tree node
Date: Thu, 5 Nov 2026 01:45:33 +0200 [thread overview]
Message-ID: <20261104234533.3044265-5-vz@kernel.org> (raw)
In-Reply-To: <20261104234533.3044265-1-vz@kernel.org>
Add Qualcomm SM8350 CAMSS device tree node to the platform dtsi file.
The CAMSS input ports will be described along with adding CSIPHY
device tree nodes, which are connected to them.
Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 110 +++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a51942c99f8a..9488b8578359 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8350-camcc.h>
#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -2830,6 +2831,115 @@ videocc: clock-controller@abf0000 {
#power-domain-cells = <1>;
};
+ camss: isp@acb4000 {
+ compatible = "qcom,sm8350-camss";
+
+ reg = <0 0x0acb4000 0 0xd000>,
+ <0 0x0acc3000 0 0xd000>,
+ <0 0x0acef000 0 0xd000>,
+ <0 0x0acd9000 0 0x2200>,
+ <0 0x0acdb200 0 0x2200>;
+ reg-names = "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_AREG_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_AREG_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_AHB_CLK>,
+ <&camcc CAM_CC_IFE_2_AREG_CLK>,
+ <&camcc CAM_CC_IFE_2_AXI_CLK>,
+ <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_2_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "gcc_hf_axi",
+ "vfe0",
+ "vfe0_ahb",
+ "vfe0_areg",
+ "vfe0_axi",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1",
+ "vfe1_ahb",
+ "vfe1_areg",
+ "vfe1_axi",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe2",
+ "vfe2_ahb",
+ "vfe2_areg",
+ "vfe2_axi",
+ "vfe2_cphy_rx",
+ "vfe2_csid",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_axi",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x440>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc IFE_2_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sm8350-camcc";
reg = <0 0x0ad00000 0 0x10000>;
--
2.51.0
next prev parent reply other threads:[~2026-11-04 23:46 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 23:45 [PATCH 0/4] media: qcom: camss: Add SM8350 CAMSS support Vladimir Zapolskiy
2026-11-04 23:45 ` [PATCH 1/4] dt-bindings: media: Add Qualcomm SM8350 CAMSS Vladimir Zapolskiy
2026-11-05 9:54 ` Bryan O'Donoghue
2026-11-05 11:13 ` Krzysztof Kozlowski
2026-11-04 23:45 ` [PATCH 2/4] media: qcom: camss: Select Titan 480 CSID offset by VFE type Vladimir Zapolskiy
2026-11-05 9:51 ` Bryan O'Donoghue
2026-11-04 23:45 ` [PATCH 3/4] media: qcom: camss: Add SM8350 CAMSS support Vladimir Zapolskiy
2026-11-05 9:53 ` Bryan O'Donoghue
2026-11-04 23:45 ` Vladimir Zapolskiy [this message]
2026-11-05 9:56 ` [PATCH 4/4] arm64: dts: qcom: sm8350: Add CAMSS device tree node Bryan O'Donoghue
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