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Wed, 4 Nov 2026 23:19:07 -0600 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Wed, 4 Nov 2026 23:19:06 -0600 Received: from xsjblevinsk51.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Wed, 4 Nov 2026 23:19:06 -0600 From: Ben Levinsky To: , , , , , CC: , , , , , , Subject: [PATCH v2 3/6] dt-bindings: mailbox: Add AMD PL Mailbox IP Date: Wed, 4 Nov 2026 21:18:59 -0800 Message-ID: <20261105051902.1646651-4-ben.levinsky@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261105051902.1646651-1-ben.levinsky@amd.com> References: <20261105051902.1646651-1-ben.levinsky@amd.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|DS0PR12MB8199:EE_ X-MS-Office365-Filtering-Correlation-Id: e9b3c279-9de3-482a-ec0c-08df3afc53c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|23010399003|30052699003|1800799024|10067099003|22082099003|18002099003|3023799007|13003099007|56012099006|11063799006|261026121527099003|261026140227099003|261028144727099003|261021135927099003|261022105027099003|261021121427099003|261102123227099003|261009223027099003; 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The Mailbox is a soft IP core instantiated in programmable logic, and the same SoC can carry different versions of it, so it is not a SoC block. Like other PL soft IP bindings, use a single compatible that names the IP core and its version, amd,pl-mailbox-2.1. "pl" distinguishes it from the IPI hardware that can also act as a mailbox. Define the transmit and receive channel indices together with the register aperture, interrupt, and interface clock. Describe the FIFO depth chosen for each IP instance when the design is synthesized. It cannot be read from the registers, and the driver needs it to size received messages. Assisted-by: Claude:claude-opus-5.5 Signed-off-by: Ben Levinsky --- .../bindings/mailbox/amd,pl-mailbox-2.1.yaml | 73 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/amd,pl-mailbox-2.1.yaml diff --git a/Documentation/devicetree/bindings/mailbox/amd,pl-mailbox-2.1.yaml b/Documentation/devicetree/bindings/mailbox/amd,pl-mailbox-2.1.yaml new file mode 100644 index 000000000000..dc16a2e1142b --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/amd,pl-mailbox-2.1.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/amd,pl-mailbox-2.1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Programmable Logic Mailbox IP + +maintainers: + - Ben Levinsky + +description: | + The AMD Programmable Logic Mailbox IP provides bidirectional message passing + between two processor-facing interfaces. Each interface writes messages to + a send FIFO and reads messages from a receive FIFO. The register aperture, + interrupt, and clock described by a node belong to one processor-facing + interface. Channel 0 represents transmit and channel 1 represents receive + for that interface. + + The Mailbox is a soft IP core instantiated in programmable logic, not a + SoC block, so the compatible names the IP core and its version (2.1). + The "pl" part distinguishes it from the IPI hardware that can also be + used as a mailbox. + +properties: + compatible: + const: amd,pl-mailbox-2.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + amd,pl-mailbox-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 16 + maximum: 8192 + default: 16 + description: + Depth of the send and receive FIFOs in 32-bit words. The depth is the + C_MAILBOX_DEPTH parameter chosen for each IP instance when the design + is synthesized, so instances in one design can differ, and it cannot + be read from the registers. Must match the synthesized depth. + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + + mailbox@b2060000 { + compatible = "amd,pl-mailbox-2.1"; + reg = <0xb2060000 0x10000>; + interrupts = ; + clocks = <&pl_clk>; + amd,pl-mailbox-depth = <16>; + #mbox-cells = <1>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 1e3f9f2751fe..3722a66b9960 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1306,6 +1306,12 @@ S: Supported T: git https://gitlab.freedesktop.org/agd5f/linux.git F: drivers/gpu/drm/amd/pm/ +AMD PROGRAMMABLE LOGIC MAILBOX DRIVER +M: Ben Levinsky +L: linux-kernel@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mailbox/amd,pl-mailbox-2.1.yaml + AMD PSTATE DRIVER M: Huang Rui M: Mario Limonciello -- 2.34.1