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[93.34.90.148]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4b56f02386bsm58869885e9.7.2026.11.05.04.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 04:11:28 -0800 (PST) From: Christian Marangi To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v10 3/5] clk: en7523: protect concurrent access to reset and PCI register Date: Thu, 5 Nov 2026 13:10:56 +0100 Message-ID: <20261105121059.11201-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261105121059.11201-1-ansuelsmth@gmail.com> References: <20261105121059.11201-1-ansuelsmth@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Use spinlock for concurrent access to reset and PCI register to catch case when clock is enabled/disabled while a reset is also operated at the same time. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 66 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 2baec734df9f..c05d0bfa2340 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -123,6 +123,8 @@ struct en_clk_desc { struct en_clk_gate { void __iomem *base; + /* protect SCU register */ + spinlock_t lock; struct clk_hw hw; }; @@ -130,6 +132,8 @@ struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; void __iomem *base; + /* protect SCU register */ + spinlock_t lock; struct reset_controller_dev rcdev; }; @@ -577,44 +581,78 @@ static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) static int en7523_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&cg->lock, flags); + val = readl(cg->base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); - return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); + return !!(val & REG_PCI_CONTROL_REFCLK_EN1); } static int en7523_pci_prepare(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); void __iomem *np_base = cg->base; + unsigned long flags; u32 val, mask; /* Need to pull device low before reset */ + spin_lock_irqsave(&cg->lock, flags); val = readl(np_base + REG_PCI_CONTROL); val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); writel(val, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); + usleep_range(1000, 2000); /* Enable PCIe port 1 */ + spin_lock_irqsave(&cg->lock, flags); val |= REG_PCI_CONTROL_REFCLK_EN1; writel(val, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); + usleep_range(1000, 2000); /* Reset to default */ + spin_lock_irqsave(&cg->lock, flags); val = readl(np_base + REG_RESET_CONTROL1); mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | REG_RESET_CONTROL_PCIEHB; writel(val & ~mask, np_base + REG_RESET_CONTROL1); + spin_unlock_irqrestore(&cg->lock, flags); + usleep_range(1000, 2000); + + spin_lock_irqsave(&cg->lock, flags); + val = readl(np_base + REG_RESET_CONTROL1); writel(val | mask, np_base + REG_RESET_CONTROL1); + spin_unlock_irqrestore(&cg->lock, flags); + msleep(100); + + spin_lock_irqsave(&cg->lock, flags); + val = readl(np_base + REG_RESET_CONTROL1); writel(val & ~mask, np_base + REG_RESET_CONTROL1); + spin_unlock_irqrestore(&cg->lock, flags); + usleep_range(5000, 10000); /* Release device */ + spin_lock_irqsave(&cg->lock, flags); mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val & ~mask, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); + usleep_range(1000, 2000); + + spin_lock_irqsave(&cg->lock, flags); + val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); + msleep(250); return 0; @@ -624,11 +662,14 @@ static void en7523_pci_unprepare(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); void __iomem *np_base = cg->base; + unsigned long flags; u32 val; + spin_lock_irqsave(&cg->lock, flags); val = readl(np_base + REG_PCI_CONTROL); val &= ~REG_PCI_CONTROL_REFCLK_EN1; writel(val, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); } static struct clk_hw *en7523_register_pcie_clk(struct device *dev, @@ -646,6 +687,7 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, return NULL; cg->base = np_base; + spin_lock_init(&cg->lock); cg->hw.init = &init; if (init.ops->unprepare) @@ -660,10 +702,15 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, static int en7581_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + unsigned long flags; u32 val, mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; + + spin_lock_irqsave(&cg->lock, flags); val = readl(cg->base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); + return (val & mask) == mask; } @@ -671,11 +718,15 @@ static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); void __iomem *np_base = cg->base; + unsigned long flags; u32 val, mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; + + spin_lock_irqsave(&cg->lock, flags); val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); return 0; } @@ -684,11 +735,16 @@ static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); void __iomem *np_base = cg->base; + unsigned long flags; u32 val, mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; + + spin_lock_irqsave(&cg->lock, flags); val = readl(np_base + REG_PCI_CONTROL); writel(val & ~mask, np_base + REG_PCI_CONTROL); + spin_unlock_irqrestore(&cg->lock, flags); + usleep_range(1000, 2000); } @@ -791,18 +847,21 @@ static int en7523_reset_update(struct reset_controller_dev *rcdev, u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK]; void __iomem *addr = rst_data->base + offset; bool inverted = false; + unsigned long flags; u32 val; /* For PCIC reset logic is inverted, 0:assert 1:deassert */ if (offset == REG_NP_SCU_PCIC) inverted = true; + spin_lock_irqsave(&rst_data->lock, flags); val = readl(addr); if (assert ^ inverted) val |= BIT(id % RST_NR_PER_BANK); else val &= ~BIT(id % RST_NR_PER_BANK); writel(val, addr); + spin_unlock_irqrestore(&rst_data->lock, flags); return 0; } @@ -826,13 +885,17 @@ static int en7523_reset_status(struct reset_controller_dev *rcdev, u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK]; void __iomem *addr = rst_data->base + offset; bool inverted = false; + unsigned long flags; u32 val; /* For PCIC reset logic is inverted, 0:assert 1:deassert */ if (offset == REG_NP_SCU_PCIC) inverted = true; + spin_lock_irqsave(&rst_data->lock, flags); val = readl(addr) & BIT(id % RST_NR_PER_BANK); + spin_unlock_irqrestore(&rst_data->lock, flags); + return inverted ? !val : !!val; } @@ -866,6 +929,7 @@ static int en7581_reset_register(struct device *dev, void __iomem *base, rst_data->bank_ofs = rst_reg_ofs; rst_data->idx_map = rst_map; rst_data->base = base; + spin_lock_init(&rst_data->lock); rst_data->rcdev.nr_resets = nr_resets; rst_data->rcdev.of_xlate = en7523_reset_xlate; -- 2.55.0