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Fri, 06 Nov 2026 09:56:06 -0800 (PST) Received: from hp-z640.fritz.box ([64.43.161.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-492d723283dsm4649612f8f.23.2026.11.06.09.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 09:56:05 -0800 (PST) From: Owen O'Hehir To: Alexandre Belloni , linux-rtc@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , "ziv.xu" , Conor Dooley Subject: [PATCH 1/3] dt-bindings: rtc: Add StarFive JH7110 RTC Date: Fri, 6 Nov 2026 17:55:58 +0000 Message-ID: <20261106175600.3877614-2-oo.hehir@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261106175600.3877614-1-oo.hehir@gmail.com> References: <20261106175600.3877614-1-oo.hehir@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the RTC in the always-on domain of the StarFive JH7110 SoC. Signed-off-by: Owen O'Hehir --- .../bindings/rtc/starfive,jh7110-rtc.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml b/Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml new file mode 100644 index 000000000..95edddea1 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/starfive,jh7110-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Real Time Clock + +maintainers: + - Alexandre Belloni + +description: + The RTC in the always-on domain of the StarFive JH7110 SoC. It counts BCD + time and date from a 32.768 kHz clock and has an alarm, a frequency offset + adjustment and millisecond and one-second pulse outputs. + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: starfive,jh7110-rtc + + reg: + maxItems: 1 + + interrupts: + items: + - description: Millisecond pulse + - description: One-second pulse + - description: Alarm and calibration events + + interrupt-names: + items: + - const: ms-pulse + - const: sec-pulse + - const: rtc + + clocks: + items: + - description: APB bus clock + - description: Calibration reference clock + - description: 32.768 kHz counter clock + + clock-names: + items: + - const: apb + - const: cal + - const: 32k + + resets: + items: + - description: 32.768 kHz counter domain reset + - description: APB bus reset + - description: Calibration reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + rtc@17040000 { + compatible = "starfive,jh7110-rtc"; + reg = <0x17040000 0x10000>; + interrupts = <10>, <11>, <12>; + interrupt-names = "ms-pulse", "sec-pulse", "rtc"; + clocks = <&aoncrg JH7110_AONCLK_RTC_APB>, + <&aoncrg JH7110_AONCLK_RTC_CAL>, + <&aoncrg JH7110_AONCLK_RTC_32K>; + clock-names = "apb", "cal", "32k"; + resets = <&aoncrg JH7110_AONRST_RTC_32K>, + <&aoncrg JH7110_AONRST_RTC_APB>, + <&aoncrg JH7110_AONRST_RTC_CAL>; + }; -- 2.43.0