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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b3757214cbsm10120176c88.13.2026.11.08.22.56.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 22:56:23 -0800 (PST) From: Joey Lu To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Catalin Marinas , Jacky Huang , Shan-Chun Hung , Hui-Ping Chen , Joey Lu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v8 2/4] arm64: dts: nuvoton: ma35d1: add USB controllers and dual-port PHY node Date: Mon, 9 Nov 2026 14:56:04 +0800 Message-ID: <20261109065606.62641-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261109065606.62641-1-a0987203069@gmail.com> References: <20261109065606.62641-1-a0987203069@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the USB subsystem nodes for the MA35D1 SoC and boards: - usb_phy: standalone PHY node with #phy-cells = <1>, covering both the OTG port (PHY0, index 0) and the host-only port (PHY1, index 1). Uses nuvoton,sys phandle and HUSBH0_GATE clock per the binding. - usb (DWC2 gadget, USB0): phys = <&usb_phy 0>, dr_mode = peripheral. - ehci0/ohci0 (USB0 host): phys = <&usb_phy 0>, companion pairing. - ehci1/ohci1 (USB1 host): phys = <&usb_phy 1>. Board files (ma35d1-som-256m.dts, ma35d1-iot-512m.dts) add pinctrl for VBUSVLD, PWREN and OVC signals and enable all USB nodes. Signed-off-by: Joey Lu Reviewed-by: Jacky Huang --- .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 36 ++++++++++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 36 ++++++++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 65 +++++++++++++++++++ 3 files changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts index 78534d613486..b2f25de2ae44 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -97,6 +97,16 @@ pinctrl_uart14: uart14-pins { power-source = <1>; }; }; + + hsusb-grp { + pinctrl_hsusb: hsusb-pins { + nuvoton,pins = <5 15 1>, /* VBUSVLD */ + <11 12 9>, /* PWREN */ + <11 13 9>; /* OVC */ + bias-disable; + power-source = <1>; + }; + }; }; &uart0 { @@ -151,3 +161,29 @@ eth_phy1: ethernet-phy@1 { reg = <1>; }; }; + +&usb_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hsusb>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts index a029b660e8dc..58349470bc64 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -100,6 +100,16 @@ pinctrl_uart16: uart16-pins { power-source = <1>; }; }; + + hsusb-grp { + pinctrl_hsusb: hsusb-pins { + nuvoton,pins = <5 15 1>, /* VBUSVLD */ + <11 12 9>, /* PWREN */ + <11 13 9>; /* OVC */ + bias-disable; + power-source = <1>; + }; + }; }; &uart0 { @@ -153,3 +163,29 @@ eth_phy1: ethernet-phy@1 { reg = <1>; }; }; + +&usb_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hsusb>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi index 7228ad4735b5..72a1659207fa 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -76,6 +76,14 @@ IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ interrupt-parent = <&gic>; }; + usb_phy: usb-phy { + compatible = "nuvoton,ma35d1-usb2-phy"; + clocks = <&clk HUSBH0_GATE>; + nuvoton,sys = <&sys>; + #phy-cells = <1>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -431,5 +439,62 @@ mdio1: mdio { #size-cells = <0>; }; }; + + usb: usb@40200000 { + compatible = "snps,dwc2"; + reg = <0x0 0x40200000 0x0 0x1000>; + interrupts = ; + clocks = <&clk USBD_GATE>; + clock-names = "otg"; + phys = <&usb_phy 0>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <0x100>; + g-tx-fifo-size = <256 256 64 64 64 32 32 32>; + status = "disabled"; + }; + + ehci0: usb@40140000 { + compatible = "generic-ehci"; + reg = <0x0 0x40140000 0x0 0x1000>; + interrupts = ; + clocks = <&clk HUSBH0_GATE>; + phys = <&usb_phy 0>; + phy-names = "usb"; + companion = <&ohci0>; + status = "disabled"; + }; + + ehci1: usb@401c0000 { + compatible = "generic-ehci"; + reg = <0x0 0x401c0000 0x0 0x1000>; + interrupts = ; + clocks = <&clk HUSBH1_GATE>; + phys = <&usb_phy 1>; + phy-names = "usb"; + companion = <&ohci1>; + status = "disabled"; + }; + + ohci0: usb@40150000 { + compatible = "generic-ohci"; + reg = <0x0 0x40150000 0x0 0x1000>; + interrupts = ; + clocks = <&clk HUSBH0_GATE>; + phys = <&usb_phy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@401d0000 { + compatible = "generic-ohci"; + reg = <0x0 0x401d0000 0x0 0x1000>; + interrupts = ; + clocks = <&clk HUSBH1_GATE>; + phys = <&usb_phy 1>; + phy-names = "usb"; + status = "disabled"; + }; }; }; -- 2.43.0