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Mon, 09 Nov 2026 17:36:58 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2edb6d9efd6sm3399055ad.50.2026.11.09.17.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 17:36:57 -0800 (PST) From: Rosen Penev To: Thomas Bogendoerfer , Stephen Boyd , Brian Masney , Jerome Brunet , Alban Bedel , Antony Pavlov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/6] dt-bindings: clock: ath79: add the PCIe PLL clock Date: Mon, 9 Nov 2026 17:36:44 -0800 Message-ID: <20261110013646.1582970-5-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261110013646.1582970-1-rosenp@gmail.com> References: <20261110013646.1582970-1-rosenp@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add an ID for the PCIe PLL, which AR724x, AR934x, QCA953x, QCA955x and QCA956x have, so the PCIe host controller nodes can reference it. Signed-off-by: Rosen Penev --- include/dt-bindings/clock/ath79-clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h index f8a98e4d206d..e4956afd151d 100644 --- a/include/dt-bindings/clock/ath79-clk.h +++ b/include/dt-bindings/clock/ath79-clk.h @@ -12,7 +12,8 @@ #define ATH79_CLK_REF 3 #define ATH79_CLK_MDIO 4 #define ATH79_CLK_UART1 5 +#define ATH79_CLK_PCIE 6 -#define ATH79_CLK_END 6 +#define ATH79_CLK_END 7 #endif /* __DT_BINDINGS_ATH79_CLK_H */ -- 2.56.0