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Mon, 09 Nov 2026 23:07:01 -0800 (PST) Received: from localhost ([2001:19f0:8000:3bef:5400:6ff:fef9:667]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b167715fd4sm2625930a91.11.2026.11.09.23.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 23:07:01 -0800 (PST) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Minas Harutyunyan , Greg Kroah-Hartman , Longbin Li , Dinh Nguyen , Paul Zimmerman , Felipe Balbi Cc: devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Yixun Lan Subject: [PATCH 4/4] riscv: dts: sophgo: Enable USB role switch on Huashan PI Date: Tue, 10 Nov 2026 15:06:25 +0800 Message-ID: <20261110070627.217946-5-inochiama@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261110070627.217946-1-inochiama@gmail.com> References: <20261110070627.217946-1-inochiama@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit As current the DWC2 support role switch on CV18XX SoCs. Enable it on Huashan PI. Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts index aedf79f47407..bf3d58c355c3 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts @@ -88,6 +88,8 @@ &uart0 { }; &usb { - dr_mode = "host"; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; status = "okay"; }; -- 2.56.0