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Tue, 10 Nov 2026 12:05:13 -0800 (PST) Received: from LRMS.tailf8556c.ts.net ([2600:4041:5024:4b00:940a:c6ea:f292:3644]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9479e76b1c3sm305084285a.16.2026.11.10.12.05.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Nov 2026 12:05:12 -0800 (PST) From: Jesse Casco To: Konrad Dybcio , Sibi Sankar Cc: Bjorn Andersson , Jassi Brar , Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: qcom: glymur: use polling mode for SCMI transfers Date: Tue, 10 Nov 2026 15:05:11 -0500 Message-ID: <20261110200511.71673-1-jesse.casco@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: <20260808172211.137577-1-jesse.casco@gmail.com> <642652c2-af5d-446c-ac1a-8099639c2588@oss.qualcomm.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Konrad, Sibi, I tracked down the timing issue on the ASUS Zenbook A16 (7.4-rc1 based, arm,no-completion-irq removed). It depends on whether PSCI cpuidle is already running when SCMI sends its first PERF (0x13) message: - CPUCP_MBOX=y: first PERF message at 0.37 s, before cpuidle starts. PERF works for the whole boot, cpuidle included. - CPUCP_MBOX=m (arm64 defconfig): first PERF message at 1.1-1.4 s, after cpuidle starts. No PERF reply ever gets a doorbell, so scmi-cpufreq and scmi-perf-domain fail with -110. BASE replies still ring. - CPUCP_MBOX=m with cpuidle.off=1: PERF works. In the failing case the firmware still writes the PERF replies (the same request through SCMI RAW message_poll returns status 0), but RX_MBOX_STAT never gets a bit, with EN=0x3 and MAP=~0, the same as in the working case. So it looks like the CPUCP decides at the first PERF exchange whether to ring for PERF, rather than a mailbox driver bug. Please consider the DT patch withdrawn. Sibi, is this a known CPUCP firmware behavior? In the meantime I could send an arm64 defconfig change building QCOM_CPUCP_MBOX in, so defconfig kernels get cpufreq on this machine, if that's acceptable. Jesse