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Tue, 10 Nov 2026 14:12:34 -0800 (PST) Received: from LRMS.tailf8556c.ts.net ([2600:4041:5024:4b00:940a:c6ea:f292:3644]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9479e73a8fasm328270285a.7.2026.11.10.14.12.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Nov 2026 14:12:33 -0800 (PST) From: Jesse Casco To: Nihal Kumar Gupta Cc: Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Suresh Vankadara , Vikram Sharma , Konrad Dybcio , Abel Vesa Subject: Re: [PATCH v2 3/6] arm64: dts: qcom: glymur: Add camera MCLK pinctrl Date: Tue, 10 Nov 2026 17:12:32 -0500 Message-ID: <20261110221232.3883-1-jesse.casco@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261015-glymur_camss_dts-v2-3-e7b1f403146f@oss.qualcomm.com> References: <20261015-glymur_camss_dts-v2-3-e7b1f403146f@oss.qualcomm.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Thu, Oct 15, 2026 at 04:22:28PM +0530, Nihal Kumar Gupta wrote: > + cam_mclk4_default: cam-mclk4-default-state { > + pins = "gpio100"; > + function = "cam_asc_mclk4"; > + drive-strength = <2>; > + bias-disable; > + }; I've been running this series on an ASUS Zenbook A16 (UX3607OA), which has an OV02C10 on MCLK4 at 19.2 MHz. With 2 mA here the sensor shows horizontal banding, and its frame period stretches by about 9%, whenever the internal DMIC clock (LPASS LPI GPIO6, 2.4 MHz) is running. The bands are already in the RAW10 frames, and the sensor test pattern is clean, so it looks like the MCLK pad itself rather than CSI or the ISP. Changing only this pin to 6 mA fixes it. A/B/A across three boots, same kernel, fixed exposure/gain, row high-pass RMS / frame period: MCLK4 mic off mic on after 2 mA 0.96 / 33.28 ms 20.44 / 36.17 ms 1.04 / 33.27 ms 6 mA 0.89 / 33.27 ms 0.90 / 33.27 ms 0.90 / 33.27 ms 2 mA 0.95 / 33.27 ms 15.33 / 34.37 ms 0.93 / 33.28 ms At 6 mA the frame timing holds steady at 33.27 ms and the image stays clean in every phase, including while the microphone is recording, which is exactly the case that couples interference into the 2 mA clock. Normal camera use with the mic on is also clean at 6 mA, so the fix holds up on real hardware, not just in the capture script. Could cam_mclk4_default use 6 mA? If you'd rather keep 2 mA in the SoC dtsi, I'll override it in the A16 board DT instead. Thanks, Jesse