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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by BN7PEPF00000093.mail.protection.outlook.com (10.167.245.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.4 via Frontend Transport; Wed, 11 Nov 2026 04:38:58 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Tue, 10 Nov 2026 22:38:57 -0600 Received: from xhdsivadur40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Tue, 10 Nov 2026 22:38:53 -0600 From: Ajay Neeli To: , , CC: , , , , , , , , , , Ajay Neeli Subject: [PATCH] dt-bindings: ufs: amd,versal2-ufs: Add ref_clk clock property Date: Wed, 11 Nov 2026 10:08:40 +0530 Message-ID: <20261111043840.906301-1-ajay.neeli@amd.com> X-Mailer: git-send-email 2.25.1 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN7PEPF00000093:EE_|CH2PR12MB9520:EE_ X-MS-Office365-Filtering-Correlation-Id: 24e35e30-dbd6-4436-edc3-08df3fadb39e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|1800799024|82310400026|36860700016|56012099006|261009223027099003|11063799006|261022075727099003|261021123027099003|261021121427099003|261022105027099003|261026140227099003|261028144727099003|261102123227099003|261026121527099003|10067099003|18002099003|6133799003; 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The AMD Versal2 UFS controller operates with a 26 MHz reference clock. UFS 3.x devices default their bRefClkFreq attribute to 26 MHz, matching the controller, so no explicit configuration is needed. However, UFS 4.0 and later devices default bRefClkFreq to 52 MHz, expecting a 52 MHz reference clock. This mismatch causes timing violations and link instability. Adding the ref_clk property allows the UFS driver to read the actual reference clock frequency from the devicetree and program the device bRefClkFreq attribute accordingly during initialization. Signed-off-by: Ajay Neeli --- .../devicetree/bindings/ufs/amd,versal2-ufs.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml index c00ec342d574..e294c0f1b0ce 100644 --- a/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml @@ -20,11 +20,12 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 2 clock-names: items: - const: core + - const: ref_clk power-domains: maxItems: 1 @@ -52,10 +53,10 @@ examples: ufs@f10b0000 { compatible = "amd,versal2-ufs"; reg = <0xf10b0000 0x1000>; - clocks = <&ufs_core_clk>; - clock-names = "core"; + clocks = <&ufs_core_clk>, <&ufs_ref_clk>; + clock-names = "core", "ref_clk"; resets = <&scmi_reset 4>, <&scmi_reset 35>; reset-names = "host", "phy"; interrupts = ; - freq-table-hz = <0 0>; + freq-table-hz = <0 0>, <26000000 26000000>; }; -- 2.43.7