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Wed, 11 Nov 2026 08:29:33 -0800 (PST) Received: from AERO17.taila7786d.ts.net ([45.95.212.227]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37520bf3e18sm34892599eec.16.2026.11.11.08.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 08:29:33 -0800 (PST) From: Pufan Jin To: Conor Dooley , Krzysztof Kozlowski , Michal Simek , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Lunn Subject: [PATCH v2 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board Date: Wed, 11 Nov 2026 11:29:17 -0500 Message-ID: <20261111162917.97532-3-cyan2254650260@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261111162917.97532-1-cyan2254650260@gmail.com> References: <20261111162917.97532-1-cyan2254650260@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add devicetree support for the ALINX AX7Z020B development board. The board is built around the ALINX AC7Z020 system on module with a Zynq-7000 (XC7Z020-2CLG400I) SoC, 1 GB DDR3 SDRAM and 32 MB QSPI flash, and provides Gigabit Ethernet (JLSemi JL2121 PHY), USB 2.0 host, MicroSD slot, dual CAN buses (SN65HVD232 transceivers on MIO 10-13), I2C RTC/EEPROM/LM75 and the serial console on UART1. DevCFG FPGA manager is also enabled. The two SMA AD inputs and the spare differential pair are wired to XADC aux channels VAUX1, VAUX9 and VAUX12. The XADC hard macro is always accessible from the PS, so expose these channels via the driver's xlnx,channels property. Link: https://www.alinx.com/ Signed-off-by: Pufan Jin --- arch/arm/boot/dts/xilinx/Makefile | 1 + .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi | 70 +++++++++ .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts | 142 ++++++++++++++++++ 3 files changed, 213 insertions(+) create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile index 9233e539b1..5c4bcd9492 100644 --- a/arch/arm/boot/dts/xilinx/Makefile +++ b/arch/arm/boot/dts/xilinx/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-alinx-ax7z020b.dtb \ zynq-cc108.dtb \ zynq-ebaz4205.dtb \ zynq-microzed.dtb \ diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi b/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi new file mode 100644 index 0000000000..1e80045cdc --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS for ALINX AC7Z020 System on Module + * + * Copyright (C) 2026 Pufan Jin + */ + +#include "zynq-7000.dtsi" + +/ { + compatible = "alinx,ac7z020", "xlnx,zynq-7000"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + pmu@f8891000 { + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&devcfg { + status = "okay"; +}; + +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00500000>; + }; + + partition@500000 { + label = "bootenv"; + reg = <0x00500000 0x00020000>; + }; + + partition@520000 { + label = "image"; + reg = <0x00520000 0x00a80000>; + }; + + partition@fa0000 { + label = "spare"; + reg = <0x00fa0000 0x01060000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts new file mode 100644 index 0000000000..472d9fcaaf --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS for ALINX AX7Z020B Development Board + * + * Copyright (C) 2026 Pufan Jin + */ + +/dts-v1/; +#include "zynq-alinx-ac7z020.dtsi" +#include +#include + +/ { + model = "ALINX AX7Z020B Development Board"; + compatible = "alinx,ax7z020b", "alinx,ac7z020", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + spi0 = &qspi; + i2c0 = &i2c0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; + }; +}; + +&adc { + xlnx,channels { + #address-cells = <1>; + #size-cells = <0>; + + /* AD1: XADC_AD1P/N, E17/D18 */ + channel@2 { + reg = <2>; + }; + + /* AD9: XADC_AD9P/N, E18/E19 */ + channel@a { + reg = <10>; + }; + + /* Spare pair: XADC_AD12P/N, F19/F20 */ + channel@d { + reg = <13>; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet_phy: ethernet-phy@1 { + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + }; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; +}; + +&sdhci0 { + bootph-all; + status = "okay"; + disable-wp; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + bootph-all; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; -- 2.56.0