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Wed, 11 Nov 2026 13:57:41 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b197ce556dsm965429a91.6.2026.11.11.13.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 13:57:41 -0800 (PST) From: Rosen Penev To: Thomas Bogendoerfer , Stephen Boyd , Brian Masney , Jerome Brunet , Alban Bedel , Antony Pavlov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/7] MIPS: ath79: stop using ATH79_CLK_END Date: Wed, 11 Nov 2026 13:57:25 -0800 Message-ID: <20261111215729.10683-4-rosenp@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261111215729.10683-1-rosenp@gmail.com> References: <20261111215729.10683-1-rosenp@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ATH79_CLK_END counts the clocks in the dt-bindings header, which means it has to change whenever a clock is added, but it is not part of the ABI. Size the clock table from the IDs that the clock code uses instead, so the define can be dropped from the header. Signed-off-by: Rosen Penev --- arch/mips/ath79/clock.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 6a8bef782186..55d8ef8c1c8c 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -25,13 +25,15 @@ #include #include "common.h" -static struct clk *clks[ATH79_CLK_END]; +#define ATH79_CLK_NUM (ATH79_CLK_MDIO + 1) + +static struct clk *clks[ATH79_CLK_NUM]; static struct clk_onecell_data clk_data = { .clks = clks, .clk_num = ARRAY_SIZE(clks), }; -static const char * const clk_names[ATH79_CLK_END] = { +static const char * const clk_names[ATH79_CLK_NUM] = { [ATH79_CLK_CPU] = "cpu", [ATH79_CLK_DDR] = "ddr", [ATH79_CLK_AHB] = "ahb", -- 2.56.0