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Petersen" , Pedro Sousa , Arnd Bergmann , AngeloGioacchino Del Regno , Bart Van Assche , Bean Huo , Stanley Jhu , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v4 3/4] scsi: ufs: dwc: Rename amd-versal2 read/write PHY API and move to dwc common file Date: Thu, 12 Nov 2026 15:56:15 +0800 Message-Id: <20261112075616.118436-4-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20261112075616.118436-1-minda.chen@starfivetech.com> References: <20261112075616.118436-1-minda.chen@starfivetech.com> Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0035.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::21) To ZQ0PR01MB1111.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:e::7) X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1111:EE_|ZQ0PR01MB0999:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f60a3ea-3904-4422-02b9-08df409274bf X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|52116014|366016|1800799024|921020|38350700014|261026140227099003|56012099006|10067099003|261022105027099003|261021121427099003|261021123027099003|261026121527099003|261028144727099003|261102130727099003|261102123227099003|261009223027099003|18002099003|22082099003|3023799007; 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Move them to ufshcd-dwc.c and rename them so that other DWC based glue drivers can reuse them. Add kernel-doc for the exported helpers. No functional change. Signed-off-by: Minda Chen --- drivers/ufs/host/ufs-amd-versal2.c | 77 +++++++----------------------- drivers/ufs/host/ufshcd-dwc.c | 61 +++++++++++++++++++++++ drivers/ufs/host/ufshcd-dwc.h | 2 + 3 files changed, 80 insertions(+), 60 deletions(-) diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c index 18a5504279e6..c969c5e6cb76 100644 --- a/drivers/ufs/host/ufs-amd-versal2.c +++ b/drivers/ufs/host/ufs-amd-versal2.c @@ -43,49 +43,6 @@ struct ufs_versal2_host { u8 ctlecompval1; }; -static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) -{ - const struct ufshcd_dme_attr_val phy_write_attrs[] = { - { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRLSB), (u8)val, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRMSB), (u8)(val >> 8), DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); -} - -static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) -{ - u32 mib_val; - int ret; - const struct ufshcd_dme_attr_val phy_read_attrs[] = { - { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); - if (ret) - return ret; - - ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); - if (ret) - return ret; - - *val = mib_val; - ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); - if (ret) - return ret; - - *val |= (mib_val << 8); - - return 0; -} - static int ufs_versal2_enable_phy(struct ufs_hba *hba) { u32 offset, reg; @@ -154,64 +111,64 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba) u32 reg; /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ - ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); + ret = ufshcd_dwc_phy_reg_read(hba, FAST_FLAGS(0), ®); if (ret) return ret; reg |= MPHY_FAST_RX_AFE_CAL; - ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); + ret = ufshcd_dwc_phy_reg_write(hba, FAST_FLAGS(0), reg); if (ret) return ret; - ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); + ret = ufshcd_dwc_phy_reg_read(hba, FAST_FLAGS(1), ®); if (ret) return ret; reg |= MPHY_FAST_RX_AFE_CAL; - ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); + ret = ufshcd_dwc_phy_reg_write(hba, FAST_FLAGS(1), reg); if (ret) return ret; /* Program ATT and CTLE compensation values */ if (host->attcompval0) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0); + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0); if (ret) return ret; } if (host->attcompval1) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1); + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1); if (ret) return ret; } if (host->ctlecompval0) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0); + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0); if (ret) return ret; } if (host->ctlecompval1) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1); + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1); if (ret) return ret; } - ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); + ret = ufshcd_dwc_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); if (ret) return ret; reg |= MPHY_FW_CALIB_CFG_VAL; - ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); + ret = ufshcd_dwc_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); if (ret) return ret; - ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); + ret = ufshcd_dwc_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); if (ret) return ret; reg |= MPHY_FW_CALIB_CFG_VAL; - return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); + return ufshcd_dwc_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); } static int ufs_versal2_phy_init(struct ufs_hba *hba) @@ -376,7 +333,7 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_ for (lane = 0; lane < activelanes; lane++) { time_left = TIMEOUT_MICROSEC; - ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret = ufshcd_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; @@ -386,12 +343,12 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_ else reg &= ~MPHY_RX_OVRD_VAL; - ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret = ufshcd_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; do { - ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); + ret = ufshcd_dwc_phy_reg_read(hba, RX_PCS_OUT(lane), ®); if (ret) return ret; @@ -453,12 +410,12 @@ static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_ch /* Remove rx_req override */ for (lane = 0; lane < dev_req_params->lane_tx; lane++) { - ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret = ufshcd_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; reg &= ~MPHY_RX_OVRD_EN; - ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret = ufshcd_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; } diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c index 21b1cf912dcc..fa6ef641e4c1 100644 --- a/drivers/ufs/host/ufshcd-dwc.c +++ b/drivers/ufs/host/ufshcd-dwc.c @@ -15,6 +15,67 @@ #include "ufshcd-dwc.h" #include "ufshci-dwc.h" +/** + * ufshcd_dwc_phy_reg_write() - write a DWC M-PHY register through the CR port + * @hba: per adapter instance + * @addr: 32-bit PHY register address, only the low 16 bits are used + * @val: 32-bit value to write, only the low 16 bits are used + * + * Return: 0 on success, non-zero value on failure. + */ +int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) +{ + const struct ufshcd_dme_attr_val phy_write_attrs[] = { + { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRLSB), (u8)val, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRMSB), (u8)(val >> 8), DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); +} +EXPORT_SYMBOL(ufshcd_dwc_phy_reg_write); + +/** + * ufshcd_dwc_phy_reg_read() - read a DWC M-PHY register through the CR port + * @hba: per adapter instance + * @addr: 32-bit PHY register address, only the low 16 bits are used + * @val: 32-bit read return value pointer + * + * Return: 0 on success, non-zero value on failure. + */ +int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) +{ + u32 mib_val; + int ret; + const struct ufshcd_dme_attr_val phy_read_attrs[] = { + { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); + if (ret) + return ret; + + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); + if (ret) + return ret; + + *val = mib_val; + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); + if (ret) + return ret; + + *val |= (mib_val << 8); + + return 0; +} +EXPORT_SYMBOL(ufshcd_dwc_phy_reg_read); + int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n) { diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h index c618bb914904..076076903730 100644 --- a/drivers/ufs/host/ufshcd-dwc.h +++ b/drivers/ufs/host/ufshcd-dwc.h @@ -68,4 +68,6 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status); int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n); +int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val); +int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val); #endif /* End of Header */ -- 2.17.1