Re: [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores

[Conor Dooley <conor@kernel.org>]

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On Fri, Nov 13, 2026 at 03:11:41PM +0800, Mina Hui-Min Chou wrote:
> The Andes cache errata probe only runs on AX45MP: it matches
> ANDES_AX45MP_MARCHID/MIMPID and then asks the Andes SBI extension
> whether IOCP is missing. Other Andes cores that need CCTL-based cache
> maintenance, such as the A27L2, which has neither IOCP nor Zicbom, are
> silently skipped.
> 
> The IOCP_SW_WORKAROUND SBI call cannot simply be used on every Andes
> core: OpenSBI checks the IOCP bit in mmsc_cfg[47], which only exists on
> RV64 cores. RV32 cores such as the A45MP report IOCP in mmsc_cfg2
> instead, and cores such as the A25/A27 do not support IOCP at all.
> 
> Keep the existing SBI-based check for AX45MP. On other Andes cores, use
> the Andes CCTL operations for cache maintenance when the core does not
> implement Zicbom.
> 
> As the probe is no longer only about IOCP, rename errata_probe_iocp()
> to errata_probe_andes_cache(), ERRATA_ANDES_NO_IOCP to
> ERRATA_ANDES_CACHE, and the ERRATA_ANDES prompt from "Andes AX45MP
> errata" to "Andes errata".
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  arch/riscv/Kconfig.errata                    |  2 +-
>  arch/riscv/errata/andes/errata.c             | 13 +++++++------
>  arch/riscv/include/asm/errata_list_vendors.h |  2 +-
>  3 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 3c43e065aa01..ca8e52bee497 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -1,7 +1,7 @@
>  menu "CPU errata selection"
>  
>  config ERRATA_ANDES
> -	bool "Andes AX45MP errata"
> +	bool "Andes errata"
>  	depends on RISCV_SBI
>  	help
>  	  All Andes errata Kconfig depend on this Kconfig. Disabling
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index dcc9d1ee5ffd..530d2df216e0 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -39,7 +39,7 @@ static long ax45mp_iocp_sw_workaround(void)
>  	return ret.error ? 0 : ret.value;
>  }
>  
> -static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
> +static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)

Just call it probe so that you dont rename it again when the next
erratum shows up?

>  {
>  	static bool done;
>  
> @@ -51,11 +51,12 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
>  
>  	done = true;
>  
> -	if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
> -		return;
> -
> -	if (!ax45mp_iocp_sw_workaround())
> +	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
> +		if (!ax45mp_iocp_sw_workaround())
> +			return;
> +	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
>  		return;
> +	}

Is this correct? The code goes on to always mark noncoherent stuff
supported, so this means that every andes device must then support
noncoherent. The commit message's wording isn't that strong.

>  
>  	/* Set this just to make core cbo code happy */

This comment is no longer accurate because you gave this value special
meaning elsewhere in the series.
That patch needs to change this comment.

Cheers,
Conor.

>  	riscv_cbom_block_size = 1;
> @@ -69,7 +70,7 @@ void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct al
>  	BUILD_BUG_ON(ERRATA_ANDES_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
>  
>  	if (stage == RISCV_ALTERNATIVES_BOOT)
> -		errata_probe_iocp(stage, archid, impid);
> +		errata_probe_andes_cache(stage, archid, impid);
>  
>  	/* we have nothing to patch here ATM so just return back */
>  }
> diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h
> index 02b5ab0d23a8..d2fbef69f421 100644
> --- a/arch/riscv/include/asm/errata_list_vendors.h
> +++ b/arch/riscv/include/asm/errata_list_vendors.h
> @@ -4,7 +4,7 @@
>  #define ASM_ERRATA_LIST_VENDORS_H
>  
>  #ifdef CONFIG_ERRATA_ANDES
> -#define	ERRATA_ANDES_NO_IOCP 0
> +#define	ERRATA_ANDES_CACHE 0
>  #define	ERRATA_ANDES_NUMBER 1
>  #endif
>  
> -- 
> 2.34.1
> 

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