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Fri, 13 Nov 2026 04:18:55 -0800 (PST) Received: from threads.localdomain ([84.70.166.92]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c605e5b2fsm5167103f8f.40.2026.11.13.04.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 04:18:54 -0800 (PST) From: Lucas Tanure To: xianwei.zhao@amlogic.com, Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/7] dt-bindings: net: add amlogic,t7-dwmac Date: Fri, 13 Nov 2026 12:18:47 +0000 Message-ID: <20261113121852.334604-3-tanure@linux.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261113121852.334604-1-tanure@linux.com> References: <20261113121852.334604-1-tanure@linux.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The T7 has the same ethernet glue as the G12A but needs two clocks of its own. The controller reaches memory through a pipeline stage with its own gate; nothing else claims it, so it is switched off as unused and transfers never finish. The glue registers share a gate with the MDIO multiplexer, which probes after the controller has programmed them: the writes are lost and the port keeps the bootloader's delays. With a newer core, a clock list of its own and delays that follow ethernet-controller.yaml, the T7 gets a binding of its own: the PHY adds the 2ns, and only the receive delay line offers fine tuning, so only rx-internal-delay-ps is valid here. Signed-off-by: Lucas Tanure --- .../bindings/net/amlogic,t7-dwmac.yaml | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/amlogic,t7-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/amlogic,t7-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,t7-dwmac.yaml new file mode 100644 index 000000000000..9b7c3864cd29 --- /dev/null +++ b/Documentation/devicetree/bindings/net/amlogic,t7-dwmac.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/amlogic,t7-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 DWMAC Ethernet controller + +maintainers: + - Lucas Tanure + +# The select keeps this schema from matching every "snps,dwmac-5.10a" node. +select: + properties: + compatible: + contains: + const: amlogic,t7-dwmac + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - const: amlogic,t7-dwmac + - const: snps,dwmac-5.10a + + reg: + items: + - description: registers of the DWMAC controller + - description: the glue registers PRG_ETH0 and PRG_ETH1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + + clocks: + items: + - description: GMAC main clock + - description: First parent clock of the internal mux + - description: Second parent clock of the internal mux + - description: + clock of the pipeline stage inserted in the bus path between + the controller and the DRAM. Without it, the controller cannot + complete DMA transfers. + - description: + APB clock of the glue registers PRG_ETH0 and PRG_ETH1. + Without it, they read as zero and ignore writes. + + clock-names: + items: + - const: stmmaceth + - const: clkin0 + - const: clkin1 + - const: pipeline + - const: pclk + + power-domains: + maxItems: 1 + + rx-internal-delay-ps: + description: + Fine tuning of the RX clock, added on top of the delays that + phy-mode describes. The PHY adds the 2ns RGMII delays, see + ethernet-controller.yaml. + default: 0 + maximum: 3000 + multipleOf: 200 + + # The TX clock has no fine tuning, its only step is a quarter of the + # clock period, the full 2ns at 1Gbit/s. The PHY adds the TX delay, so + # the property is not accepted. + tx-internal-delay-ps: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - phy-mode + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + ethernet@fdc00000 { + compatible = "amlogic,t7-dwmac", "snps,dwmac-5.10a"; + reg = <0xfdc00000 0x10000>, <0xfe024000 0x8>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clkc_periphs CLKID_SYS_ETH>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&mpll CLKID_MPLL2>, + <&clkc_periphs CLKID_SYS_AMPIPE_ETH>, + <&clkc_periphs CLKID_SYS_ETHPHY>; + clock-names = "stmmaceth", "clkin0", "clkin1", "pipeline", "pclk"; + power-domains = <&pwrc PWRC_T7_ETH_ID>; + phy-mode = "rgmii-id"; + }; -- 2.56.1