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charset="utf-8" Message-Id: <20261115-iep2-v2-3-3d8798cd9a55@gmail.com> References: <20261115-iep2-v2-0-3d8798cd9a55@gmail.com> In-Reply-To: <20261115-iep2-v2-0-3d8798cd9a55@gmail.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hans Verkuil , Nicolas Dufresne , Alex Bee , Arun Iyengar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794732461; l=1739; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=WgCd6FsHVVdbiiKnG9YJDyBq5Nk8EKW+LFZEF7P5gec=; b=6xBonRNfOzrdmycrpmbKrjOX2pQiyC7WGlJ6F8Ian2KtFAr7aMzhBQ1KnTpM9GOStA+Qj7+Zm FswE3oDVt7WDd1Ps6cCafOaqJUFkyIOzjLX/DJAq44rHYFFQzO6MgSn X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Reply-To: aiyengar1990@gmail.com Content-Transfer-Encoding: 7bit From: Arun Iyengar Add the IEP2 deinterlacer and its IOMMU to the RK3588 base dtsi. Both share GIC SPI 117 and sit in the VDPU power domain. Addresses, clocks, resets and the interrupt are taken from the Rockchip BSP rk3588s.dtsi (develop-6.1). Signed-off-by: Arun Iyengar --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index aa69fd3793fd..5297519bd251 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1397,6 +1397,28 @@ vepu121_3_mmu: iommu@fdbac800 { #iommu-cells = <0>; }; + iep: deinterlace@fdbb0000 { + compatible = "rockchip,rk3588-iep2", "rockchip,rk3568-iep2"; + reg = <0x0 0xfdbb0000 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>; + reset-names = "axi", "ahb", "core"; + power-domains = <&power RK3588_PD_VDPU>; + iommus = <&iep_mmu>; + }; + + iep_mmu: iommu@fdbb0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdbb0800 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + vdec0: video-codec@fdc38000 { compatible = "rockchip,rk3588-vdec"; reg = <0x0 0xfdc38000 0x0 0x100>, -- 2.55.0