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Sat, 14 Nov 2026 22:11:23 -0800 (PST) Received: from jernej-laptop ([2a00:ee2:6a02:9300:bb69:6bcf:1b11:e85b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb5ba25b50sm139331075e9.14.2026.11.14.22.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2026 22:11:23 -0800 (PST) From: Jernej Skrabec To: Chen-Yu Tsai , Samuel Holland Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, sboyd@kernel.org, Andre Przywara , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 2/8] clk: sunxi-ng: de2: Export register regmap for DE33 Date: Sun, 15 Nov 2026 07:10:56 +0100 Message-ID: <20261115061102.229680-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261115061102.229680-1-jernej.skrabec@gmail.com> References: <20261115061102.229680-1-jernej.skrabec@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The DE33 clock driver presets the plane mapping, which is not something that a clock driver should do. Remove that and export the mapping registers through a regmap instead, so the DRM driver can set them properly. Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 43 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 6ec6c0dc4c26..f17570efafaa 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "ccu_common.h" @@ -283,6 +284,36 @@ static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = { .num_resets = ARRAY_SIZE(sun50i_h616_de33_resets), }; +/* + * Add a regmap for the DE33 plane driver to access plane + * mapping registers. + * Only these registers are allowed to be written, to prevent + * overriding clock and reset configuration. + */ + +#define SUN50I_DE33_CHN2CORE_REG 0x24 +#define SUN50I_DE33_PORT12CHN_REG 0x2c + +static const struct regmap_range sun8i_de2_ccu_regmap_accessible_ranges[] = { + regmap_reg_range(SUN50I_DE33_CHN2CORE_REG, SUN50I_DE33_PORT12CHN_REG), +}; + +static const struct regmap_access_table sun8i_de2_ccu_regmap_accessible_table = { + .yes_ranges = sun8i_de2_ccu_regmap_accessible_ranges, + .n_yes_ranges = ARRAY_SIZE(sun8i_de2_ccu_regmap_accessible_ranges), +}; + +static const struct regmap_config sun8i_de2_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = SUN50I_DE33_PORT12CHN_REG, + + /* other devices have no business accessing other registers */ + .wr_table = &sun8i_de2_ccu_regmap_accessible_table, + .rd_table = &sun8i_de2_ccu_regmap_accessible_table, +}; + static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct clk *bus_clk, *mod_clk; @@ -336,13 +367,19 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) } /* - * The DE33 requires these additional (unknown) registers set + * The DE33 requires these additional plane mapping registers set * during initialisation. */ if (of_device_is_compatible(pdev->dev.of_node, "allwinner,sun50i-h616-de33-clk")) { - writel(0, reg + 0x24); - writel(0x0000a980, reg + 0x28); + struct regmap *regmap; + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun8i_de2_ccu_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + goto err_assert_reset; + } } ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); -- 2.43.0