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Sun, 15 Nov 2026 09:11:53 -0800 (PST) Received: from jernej-laptop ([2a00:ee2:6a02:9300:bb69:6bcf:1b11:e85b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb4e2538b9sm501415845e9.1.2026.11.15.09.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Nov 2026 09:11:53 -0800 (PST) From: Jernej Skrabec To: Chen-Yu Tsai , Samuel Holland Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , James Hilliard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 1/2] arm64: dts: allwinner: sun50i-h6: Add AC200 companion chip Date: Sun, 15 Nov 2026 18:11:47 +0100 Message-ID: <20261115171148.37784-2-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261115171148.37784-1-jernej.skrabec@gmail.com> References: <20261115171148.37784-1-jernej.skrabec@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Every H6 package contains an X-Powers AC200 die next to the SoC. It is controlled over I2C3 (PB17/PB18), takes its 24 MHz reference clock from PWM1 (PB19), and its Fast Ethernet PHY connects to the EMAC through the RMII pins on port A. Describe these parts in the SoC dtsi: - the I2C3 controller with the AC200 at address 0x10 as its child, - a pwm-clock that runs PWM1 in bypass mode at 24 MHz as the AC200 input clock, - the I2C3, PWM1 and RMII pin groups, - the EPHY calibration value in the SID. Everything stays disabled. Boards that use the AC200 enable the pwm-clock, the PWM and I2C3 controllers and describe the PHY package on their MDIO bus. Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 48c771223af4..5e48b35d13de 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -17,6 +17,16 @@ / { #address-cells = <1>; #size-cells = <1>; + ac200_clk: ac200-clk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + pwms = <&pwm 1 42 0>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -314,6 +324,10 @@ ths_calibration: thermal-sensor-calibration@14 { cpu_speed_grade: cpu-speed-grade@1c { reg = <0x1c 0x4>; }; + + ephy_calibration: ephy-calibration@2c { + reg = <0x2c 0x1>; + }; }; timer@3009000 { @@ -388,6 +402,11 @@ i2c2_pins: i2c2-pins { function = "i2c2"; }; + i2c3_pins: i2c3-pins { + pins = "PB17", "PB18"; + function = "i2c3"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -414,6 +433,19 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; + pwm1_pin: pwm1-pin { + pins = "PB19"; + function = "pwm1"; + }; + + /omit-if-no-ref/ + rmii_pins: rmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", "PA4", + "PA5", "PA6", "PA7", "PA8", "PA9"; + function = "emac"; + drive-strength = <40>; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC3"; @@ -626,6 +658,27 @@ i2c2: i2c@5002800 { #size-cells = <0>; }; + i2c3: i2c@5002c00 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + /* AC200 is co-packaged with the H6 die. */ + ac200: mixed-signal@10 { + compatible = "x-powers,ac200"; + reg = <0x10>; + clocks = <&ac200_clk>; + }; + }; + spi0: spi@5010000 { compatible = "allwinner,sun50i-h6-spi", "allwinner,sun8i-h3-spi"; -- 2.43.0