[PATCH v2 2/2] i2c: tegra20: Add driver for Tegra20 I2C target controller instances

[Marc Dietrich <marvin24@gmx.de>]

Tegra20 SoC support 3 instances of the I2C target controller. It shares
ressouces with the I2C controller. Only exclusive operation as an i2c
target is supported for now.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
---
 MAINTAINERS                           |   6 +
 drivers/i2c/busses/Kconfig            |  14 +
 drivers/i2c/busses/Makefile           |   1 +
 drivers/i2c/busses/i2c-tegra-target.c | 351 ++++++++++++++++++++++++++
 4 files changed, 372 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-tegra-target.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 782389bd5cd3..e47734742cba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26894,6 +26894,12 @@ R:	Dmitry Osipenko <digetx@gmail.com>
 S:	Supported
 F:	drivers/i2c/busses/i2c-tegra.c
 
+TEGRA I2C TARGET DRIVER
+M:	Marc Dietrich <marvin24@gmx.de>
+L:	linux-tegra@vger.kernel.org
+S:	Maintained
+F:	drivers/i2c/busses/i2c-tegra-target.c
+
 TEGRA IOMMU DRIVERS
 M:	Thierry Reding <thierry.reding@kernel.org>
 R:	Krishna Reddy <vdumpa@nvidia.com>
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d7b89508311f..b8c5f9fb6c86 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1242,6 +1242,20 @@ config I2C_TEGRA_BPMP
 	  of the BPMP firmware, and this driver merely communicates with that
 	  real driver.
 
+config I2C_TEGRA_TARGET
+	tristate "NVIDIA Tegra20 I2C controller in target mode"
+	depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
+	select I2C_SLAVE
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controller embedded in NVIDIA Tegra20 SoCs when it is used as
+	  an I2C target (slave) on the bus. A controller instance that is
+	  described with the target compatible in the device tree cannot be
+	  used as an I2C controller at the same time.
+
+	  This driver can also be built as a module. If so, the module will
+	  be called i2c-tegra-target.
+
 config I2C_UNIPHIER
 	tristate "UniPhier FIFO-less I2C controller"
 	depends on ARCH_UNIPHIER || COMPILE_TEST
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3755c54b3d82..724931114412 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -119,6 +119,7 @@ obj-$(CONFIG_I2C_SUN6I_P2WI)	+= i2c-sun6i-p2wi.o
 obj-$(CONFIG_I2C_SYNQUACER)	+= i2c-synquacer.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_TEGRA_BPMP)	+= i2c-tegra-bpmp.o
+obj-$(CONFIG_I2C_TEGRA_TARGET)	+= i2c-tegra-target.o
 obj-$(CONFIG_I2C_UNIPHIER)	+= i2c-uniphier.o
 obj-$(CONFIG_I2C_UNIPHIER_F)	+= i2c-uniphier-f.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
diff --git a/drivers/i2c/busses/i2c-tegra-target.c b/drivers/i2c/busses/i2c-tegra-target.c
new file mode 100644
index 000000000000..bca63cc89fce
--- /dev/null
+++ b/drivers/i2c/busses/i2c-tegra-target.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Driver for the I2C target controller on Tegra20 SoC
+ *
+ * Copyright (C) 2026 Marc Dietrich
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/reset.h>
+
+#define I2C_CNFG				0x000
+#define I2C_CNFG_DEBOUNCE_CNT			GENMASK(14, 12)
+#define I2C_CNFG_PACKET_MODE_EN			BIT(10)
+#define I2C_CNFG_NEW_MASTER_FSM			BIT(11)
+
+#define I2C_SL_CNFG				0x020
+#define I2C_SL_CNFG_NACK			BIT(1)
+#define I2C_SL_CNFG_NEWSL			BIT(2)
+
+#define I2C_SL_RCVD				0x024
+
+#define I2C_SL_STATUS				0x028
+#define I2C_SL_STATUS_RNW			BIT(1)
+#define I2C_SL_STATUS_RCVD			BIT(2)
+#define I2C_SL_STATUS_SL_IRQ			BIT(3)
+#define I2C_SL_STATUS_END_TRANS			BIT(4)
+
+#define I2C_SL_ADDR1				0x02c
+#define I2C_SL_ADDR1_7BIT_ADDR			GENMASK(6, 0)
+#define I2C_SL_ADDR2				0x030
+
+#define I2C_CLK_MULTIPLIER			8
+
+/*
+ * This delay is used for a Tegra20 specific workaround which requires the
+ * delayed acknowledge of the address byte during read access
+ */
+#define I2C_READ_ACK_DELAY_US			33
+
+/**
+ * struct tegra_i2c_target_dev - per device I2C target context
+ * @dev: device reference
+ * @adapter: core I2C layer adapter information
+ * @clocks: array of I2C controller clocks
+ * @div_clk: clock reference for div clock of I2C controller
+ * @base: ioremapped registers cookie
+ * @irq: IRQ number of the target interrupt
+ * @timings: i2c timings information like bus frequency
+ * @target: registered target client, NULL if none
+ * @running: clocks and interrupt are enabled, the registers can be accessed
+ */
+struct tegra_i2c_target_dev {
+	struct device *dev;
+	struct i2c_adapter adapter;
+
+	struct clk_bulk_data clocks[2];
+	struct clk *div_clk;
+
+	void __iomem *base;
+	unsigned int irq;
+
+	struct i2c_timings timings;
+	struct i2c_client *target;
+	bool running;
+};
+
+static u32 i2c_readl(struct tegra_i2c_target_dev *i2c_dev, unsigned int reg)
+{
+	return readl_relaxed(i2c_dev->base + reg);
+}
+
+static void i2c_writel(struct tegra_i2c_target_dev *i2c_dev, u32 val,
+		       unsigned int reg)
+{
+	writel_relaxed(val, i2c_dev->base + reg);
+
+	/* read back register to make sure that register writes completed */
+	readl_relaxed(i2c_dev->base + reg);
+}
+
+static int tegra_i2c_target_init(struct tegra_i2c_target_dev *i2c_dev)
+{
+	u32 val;
+	int err;
+
+	err = device_reset(i2c_dev->dev);
+	if (err)
+		return err;
+
+	val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
+	      FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
+	i2c_writel(i2c_dev, val, I2C_CNFG);
+
+	err = clk_set_rate(i2c_dev->div_clk,
+			   i2c_dev->timings.bus_freq_hz * I2C_CLK_MULTIPLIER);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
+		return err;
+	}
+
+	i2c_writel(i2c_dev, I2C_SL_CNFG_NEWSL, I2C_SL_CNFG);
+
+	/* only 7-bit target address is supported for now */
+	val = FIELD_PREP(I2C_SL_ADDR1_7BIT_ADDR, i2c_dev->target->addr);
+	i2c_writel(i2c_dev, val, I2C_SL_ADDR1);
+	i2c_writel(i2c_dev, 0, I2C_SL_ADDR2);
+
+	return 0;
+}
+
+static void tegra_i2c_target_deinit(struct tegra_i2c_target_dev *i2c_dev)
+{
+	/* stop acknowledging the own address */
+	i2c_writel(i2c_dev, I2C_SL_CNFG_NEWSL | I2C_SL_CNFG_NACK, I2C_SL_CNFG);
+}
+
+static int tegra_i2c_target_start(struct tegra_i2c_target_dev *i2c_dev)
+{
+	int err;
+
+	err = clk_bulk_prepare_enable(ARRAY_SIZE(i2c_dev->clocks),
+				      i2c_dev->clocks);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to enable clocks: %d\n", err);
+		return err;
+	}
+
+	err = tegra_i2c_target_init(i2c_dev);
+	if (err) {
+		clk_bulk_disable_unprepare(ARRAY_SIZE(i2c_dev->clocks),
+					   i2c_dev->clocks);
+		return err;
+	}
+
+	enable_irq(i2c_dev->irq);
+	i2c_dev->running = true;
+
+	return 0;
+}
+
+static void tegra_i2c_target_stop(struct tegra_i2c_target_dev *i2c_dev)
+{
+	if (!i2c_dev->running)
+		return;
+
+	disable_irq(i2c_dev->irq);
+	tegra_i2c_target_deinit(i2c_dev);
+	clk_bulk_disable_unprepare(ARRAY_SIZE(i2c_dev->clocks), i2c_dev->clocks);
+	i2c_dev->running = false;
+}
+
+static irqreturn_t tegra_i2c_target_isr(int irq, void *dev_id)
+{
+	struct tegra_i2c_target_dev *i2c_dev = dev_id;
+	struct i2c_client *target = i2c_dev->target;
+	bool read, new_xfer;
+	u32 status;
+	u8 val = 0xff;
+
+	status = i2c_readl(i2c_dev, I2C_SL_STATUS);
+	if (!(status & I2C_SL_STATUS_SL_IRQ))
+		return IRQ_NONE;
+
+	/* RNW is set if the controller reads from the target */
+	read = status & I2C_SL_STATUS_RNW;
+
+	/* RCVD is set if the interrupt is for the address byte */
+	new_xfer = status & I2C_SL_STATUS_RCVD;
+
+	if (!read) {
+		val = i2c_readl(i2c_dev, I2C_SL_RCVD);
+		if (new_xfer)
+			i2c_writel(i2c_dev, 0, I2C_SL_RCVD);
+	}
+
+	if (status & I2C_SL_STATUS_END_TRANS) {
+		i2c_slave_event(target, I2C_SLAVE_STOP, &val);
+
+		/* a new transfer may already have started */
+		if (!new_xfer)
+			return IRQ_HANDLED;
+	}
+
+	if (read) {
+		if (new_xfer) {
+			udelay(I2C_READ_ACK_DELAY_US);
+			i2c_slave_event(target, I2C_SLAVE_READ_REQUESTED, &val);
+		} else {
+			i2c_slave_event(target, I2C_SLAVE_READ_PROCESSED, &val);
+		}
+
+		/* send the byte and release the bus */
+		i2c_writel(i2c_dev, val, I2C_SL_RCVD);
+	} else if (new_xfer) {
+		i2c_slave_event(target, I2C_SLAVE_WRITE_REQUESTED, &val);
+	} else {
+		i2c_slave_event(target, I2C_SLAVE_WRITE_RECEIVED, &val);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int tegra_i2c_target_reg_target(struct i2c_client *target)
+{
+	struct tegra_i2c_target_dev *i2c_dev = i2c_get_adapdata(target->adapter);
+	int err;
+
+	if (i2c_dev->target)
+		return -EBUSY;
+
+	if (target->flags & I2C_CLIENT_TEN)
+		return -EAFNOSUPPORT;
+
+	i2c_dev->target = target;
+
+	err = tegra_i2c_target_start(i2c_dev);
+	if (err)
+		i2c_dev->target = NULL;
+
+	return err;
+}
+
+static int tegra_i2c_target_unreg_target(struct i2c_client *target)
+{
+	struct tegra_i2c_target_dev *i2c_dev = i2c_get_adapdata(target->adapter);
+
+	WARN_ON(!i2c_dev->target);
+
+	tegra_i2c_target_stop(i2c_dev);
+	i2c_dev->target = NULL;
+
+	return 0;
+}
+
+static u32 tegra_i2c_target_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_SLAVE;
+}
+
+static const struct i2c_algorithm tegra_i2c_target_algo = {
+	.functionality = tegra_i2c_target_func,
+	.reg_target = tegra_i2c_target_reg_target,
+	.unreg_target = tegra_i2c_target_unreg_target,
+};
+
+static int tegra_i2c_target_probe(struct platform_device *pdev)
+{
+	struct tegra_i2c_target_dev *i2c_dev;
+	int err;
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, i2c_dev);
+
+	i2c_dev->dev = &pdev->dev;
+
+	i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(i2c_dev->base))
+		return PTR_ERR(i2c_dev->base);
+
+	err = platform_get_irq(pdev, 0);
+	if (err < 0)
+		return err;
+
+	i2c_dev->irq = err;
+
+	i2c_parse_fw_timings(&pdev->dev, &i2c_dev->timings, true);
+
+	i2c_dev->clocks[0].id = "div-clk";
+	i2c_dev->clocks[1].id = "fast-clk";
+
+	err = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(i2c_dev->clocks),
+				i2c_dev->clocks);
+	if (err)
+		return dev_err_probe(&pdev->dev, err,
+				     "failed to get controller clocks\n");
+
+	i2c_dev->div_clk = i2c_dev->clocks[0].clk;
+
+	err = devm_request_irq(&pdev->dev, i2c_dev->irq, tegra_i2c_target_isr,
+			       IRQF_NO_AUTOEN, dev_name(&pdev->dev), i2c_dev);
+	if (err)
+		return dev_err_probe(&pdev->dev, err,
+				     "failed to request IRQ %u\n", i2c_dev->irq);
+
+	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
+	i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
+	i2c_dev->adapter.dev.parent = &pdev->dev;
+	i2c_dev->adapter.owner = THIS_MODULE;
+	i2c_dev->adapter.algo = &tegra_i2c_target_algo;
+	strscpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
+		sizeof(i2c_dev->adapter.name));
+
+	return devm_i2c_add_adapter(&pdev->dev, &i2c_dev->adapter);
+}
+
+static int tegra_i2c_target_suspend(struct device *dev)
+{
+	struct tegra_i2c_target_dev *i2c_dev = dev_get_drvdata(dev);
+
+	if (i2c_dev->target)
+		tegra_i2c_target_stop(i2c_dev);
+
+	return 0;
+}
+
+static int tegra_i2c_target_resume(struct device *dev)
+{
+	struct tegra_i2c_target_dev *i2c_dev = dev_get_drvdata(dev);
+
+	if (!i2c_dev->target)
+		return 0;
+
+	return tegra_i2c_target_start(i2c_dev);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(tegra_i2c_target_pm,
+				tegra_i2c_target_suspend,
+				tegra_i2c_target_resume);
+
+static const struct of_device_id tegra_i2c_target_of_match[] = {
+	{ .compatible = "nvidia,tegra20-i2c-target" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, tegra_i2c_target_of_match);
+
+static struct platform_driver tegra_i2c_target_driver = {
+	.probe = tegra_i2c_target_probe,
+	.driver = {
+		.name = "tegra-i2c-target",
+		.of_match_table = tegra_i2c_target_of_match,
+		.pm = pm_sleep_ptr(&tegra_i2c_target_pm),
+	},
+};
+module_platform_driver(tegra_i2c_target_driver);
+
+MODULE_DESCRIPTION("NVIDIA Tegra20 I2C controller driver for target mode");
+MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>");
+MODULE_LICENSE("GPL");
-- 
2.55.0