From: Clement LE GOFFIC <clement.legoffic@foss.st.com>
To: Julius Werner <jwerner@chromium.org>
Cc: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Jonathan Corbet <corbet@lwn.net>,
Gatien Chevallier <gatien.chevallier@foss.st.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Gabriel Fernandez <gabriel.fernandez@foss.st.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Le Goffic <legoffic.clement@gmail.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-perf-users@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-kernel@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 05/20] dt-bindings: memory: factorise LPDDR props into SDRAM props
Date: Thu, 24 Jul 2025 10:14:11 +0200 [thread overview]
Message-ID: <204401b4-b483-47e2-ae73-0994b39bd30c@foss.st.com> (raw)
In-Reply-To: <CAODwPW_kex5Agqxg_i-XC308scEpUJU0me55G7iZ8nB9LC0acg@mail.gmail.com>
Hi Julius,
On 7/23/25 23:48, Julius Werner wrote:
>> + Compatible strings can be either explicit vendor names and part numbers
>> + (e.g. elpida,ECB240ABACN), or generated strings of the form
>> + (lp)?ddrX-Y,Z where X, Y and Z are in lower case hexadecimal with leading
>> + zeroes and :
>> + - X is the SDRAM version (2, 3, 4, etc.)
>> + - for LPDDR :
>> + - Y is the manufacturer ID (from MR5), 2 bytes
>> + - Z is the revision ID (from MR6 and MR7), 4 bytes
>
> It's actually one byte manufacturer, two bytes revision. The YY,ZZZZ
> is supposed to represent the amount of hex digits needed.
Oh yes I see my error..
>
>> + - for DDR4 with SPD, according to JEDEC SPD4.1.2.L-6 :
>> + - Y is the manufacturer ID, 2 bytes, from bytes 320 and 321
>> + - Z is the revision ID, 1 byte, from byte 349
>
> I don't think this will identify a part unambiguously, I would expect
> the DDR revision ID to be specific to the part number. (In fact, we're
> also not sure whether manufacturer+revision identifies LPDDR parts
> unambiguously for every vendor, we just didn't have anything more to
> work with there.) I would suggest to use either `ddrX-YYYY,AAA...,ZZ`
> or `ddrX-YYYY,ZZ,AAA...` (where AAA... is the part number string from
> SPD 329-348 without the trailing spaces). The first version looks a
> bit more natural but it might get confusing on the off chance that
> someone uses a comma in a part number string.
The first one seems better indeed.
If the manufacturer put a comma in the part number we should handle it
at a software level to me and if it is a devicetree error it is up to
the devicetree writer to fix it.
What do you think ?
>
>> + The latter form can be useful when SDRAM nodes are created at runtime by
>> + boot firmware that doesn't have access to static part number information.
>
> nit: This text slightly doesn't make sense anymore when in the DDR
> case we do actually have the part number. I guess the real thing the
> bootloader wouldn't have access to is the JEDEC manufacturer ID to
> name mapping.
Yes I will update it.
>
>> + SDRAM revision ID:
>> + - LPDDR SDRAM, decoded from Mode Register 6 and 7.
>> + - DDR4 SDRAM, decoded from the SPD from bytes 349 according to
>> + JEDEC SPD4.1.2.L-6.
>
> nit: Clarify that this is always two bytes for LPDDR and always one
> byte for DDR.
Ok
>
>> + Density of SDRAM chip in megabits:
>> + - LPDDR SDRAM, decoded from Mode Register 8.
>> + - DDR4 SDRAM, decoded from the SPD from bytes 322 to 325 according to
>> + JEDEC SPD4.1.2.L-6.
>
> Are these numbers correct? I downloaded SPD4.1.2.L-6 now and it looks
> like 322 is manufacturing location and 323-324 are manufacturing date.
> (Also, I think all of these are specific to DDR4 (and possibly 5?),
> but not to earlier versions. I don't think we need to list it for
> every version, but we should at least be specific what it applies to.)
I just reopen the doc and you are right, didn't have my glasses on I guess.
Accordingly to SPD4.1.2.L-6 it the info seems in the byte 4 on bits 3~0.
Best regards,
Clément
next prev parent reply other threads:[~2025-07-24 8:17 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-23 13:05 [PATCH v4 00/20] Introduce STM32 DDR PMU for STM32MP platforms Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 01/20] bus: firewall: move stm32_firewall header file in include folder Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 02/20] dt-bindings: stm32: stm32mp25: add `access-controller-cell` property Clément Le Goffic
2025-07-23 13:41 ` Rob Herring
2025-07-23 13:49 ` Clement LE GOFFIC
2025-07-23 13:05 ` [PATCH v4 03/20] clk: stm32mp25: add firewall grant_access ops Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 04/20] arm64: dts: st: set rcc as an access-controller Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 05/20] dt-bindings: memory: factorise LPDDR props into SDRAM props Clément Le Goffic
2025-07-23 21:48 ` Julius Werner
2025-07-24 8:14 ` Clement LE GOFFIC [this message]
2025-07-24 22:33 ` Julius Werner
2025-07-25 7:06 ` Clement LE GOFFIC
2025-07-23 13:05 ` [PATCH v4 06/20] dt-bindings: memory: introduce DDR4 Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 07/20] dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 08/20] dt-binding: memory: add DDR4 channel compatible Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 09/20] dt-bindings: memory: SDRAM channel: standardise node name Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 10/20] arm64: dts: st: add LPDDR channel to stm32mp257f-dk board Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 11/20] arm64: dts: st: add DDR channel to stm32mp257f-ev1 board Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 12/20] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 13/20] perf: stm32: introduce DDRPERFM driver Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 14/20] Documentation: perf: stm32: add ddrperfm support Clément Le Goffic
2025-07-23 13:05 ` [PATCH v4 15/20] MAINTAINERS: add myself as STM32 DDR PMU maintainer Clément Le Goffic
2025-07-23 13:06 ` [PATCH v4 16/20] ARM: dts: stm32: add ddrperfm on stm32mp131 Clément Le Goffic
2025-07-23 13:06 ` [PATCH v4 17/20] ARM: dts: stm32: add ddrperfm on stm32mp151 Clément Le Goffic
2025-07-23 13:06 ` [PATCH v4 18/20] arm64: dts: st: add ddrperfm on stm32mp251 Clément Le Goffic
2025-07-23 13:06 ` [PATCH v4 19/20] arm64: dts: st: support ddrperfm on stm32mp257f-dk Clément Le Goffic
2025-07-23 13:06 ` [PATCH v4 20/20] arm64: dts: st: support ddrperfm on stm32mp257f-ev1 Clément Le Goffic
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