* [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:49 ` Krzysztof Kozlowski
2024-10-11 14:09 ` [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine Vikram Sharma
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Add bindings for qcom,sc7280-camss to support the camera subsystem
on the SC7280 platform.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../bindings/media/qcom,sc7280-camss.yaml | 440 ++++++++++++++++++
1 file changed, 440 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
new file mode 100644
index 000000000000..2552354e4999
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
@@ -0,0 +1,440 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+
+---
+$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 CAMSS ISP
+
+maintainers:
+ - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
+ - Hariram Purushothaman <hariramp@quicinc.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sc7280-camss
+
+ clocks:
+ maxItems: 32
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: csi0
+ - const: csi1
+ - const: csi2
+ - const: csi3
+ - const: csi4
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: gcc_camera_ahb
+ - const: gcc_camera_axi
+ - const: soc_ahb
+ - const: vfe0_axi
+ - const: vfe0
+ - const: vfe0_cphy_rx
+ - const: vfe1_axi
+ - const: vfe1
+ - const: vfe1_cphy_rx
+ - const: vfe2_axi
+ - const: vfe2
+ - const: vfe2_cphy_rx
+ - const: vfe0_lite
+ - const: vfe0_lite_cphy_rx
+ - const: vfe1_lite
+ - const: vfe1_lite_cphy_rx
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+
+ interrupts:
+ maxItems: 15
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domains-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@4:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@5:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ reg:
+ maxItems: 15
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - interrupt-names
+ - iommus
+ - power-domains
+ - power-domains-names
+ - reg
+ - reg-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,camcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/interconnect/qcom,sc7280.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: camss@acaf000 {
+ compatible = "qcom,sc7280-camss";
+
+ clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_2_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
+ <&clock_camcc CAM_CC_CSIPHY0_CLK>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSIPHY1_CLK>,
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSIPHY2_CLK>,
+ <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSIPHY3_CLK>,
+ <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSIPHY4_CLK>,
+ <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_2_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_2_CLK>,
+ <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_0_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_1_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
+
+ clock-names = "camnoc_axi",
+ "csi0",
+ "csi1",
+ "csi2",
+ "csi3",
+ "csi4",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_camera_ahb",
+ "gcc_camera_axi",
+ "soc_ahb",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe2_axi",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe0_lite",
+ "vfe0_lite_cphy_rx",
+ "vfe1_lite",
+ "vfe1_lite_cphy_rx";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
+
+ interconnect-names = "ahb", "hf_0";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ iommus = <&apps_smmu 0x800 0x4e0>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ power-domains-names = "ife0", "ife1", "ife2", "top";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc1000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0accf000 0x0 0x1000>,
+ <0x0 0x0ace0000 0x0 0x2000>,
+ <0x0 0x0ace2000 0x0 0x2000>,
+ <0x0 0x0ace4000 0x0 0x2000>,
+ <0x0 0x0ace6000 0x0 0x2000>,
+ <0x0 0x0ace8000 0x0 0x2000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acbd000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0accb000 0x0 0x4000>;
+
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding
2024-10-11 14:09 ` [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma
@ 2024-10-11 14:49 ` Krzysztof Kozlowski
2024-10-21 12:22 ` Vikram Sharma
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-11 14:49 UTC (permalink / raw)
To: Vikram Sharma
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Fri, Oct 11, 2024 at 07:39:25PM +0530, Vikram Sharma wrote:
> @@ -0,0 +1,440 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +
Drop blank line (that's a new finding, I would not complain except that
I expect new version, see further).
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@acaf000 {
> + compatible = "qcom,sc7280-camss";
> +
> + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
Alignment did not improve. Please carefully read DTS coding style.
> + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY0_CLK>,
> + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY1_CLK>,
> + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY2_CLK>,
> + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY3_CLK>,
> + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY4_CLK>,
> + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
> +
> + clock-names = "camnoc_axi",
> + "csi0",
Alignment did not improve. Please carefully read DTS coding style.
> + "csi1",
> + "csi2",
> + "csi3",
> + "csi4",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "gcc_camera_ahb",
> + "gcc_camera_axi",
> + "soc_ahb",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe2_axi",
> + "vfe2",
> + "vfe2_cphy_rx",
> + "vfe0_lite",
> + "vfe0_lite_cphy_rx",
> + "vfe1_lite",
> + "vfe1_lite_cphy_rx";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
Alignment did not improve. Please carefully read DTS coding style.
> +
> + interconnect-names = "ahb", "hf_0";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
Alignment did not improve. Please carefully read DTS coding style.
> + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
Alignment did not improve. Please carefully read DTS coding style.
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + iommus = <&apps_smmu 0x800 0x4e0>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
Alignment did not improve. Please carefully read DTS coding style.
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + power-domains-names = "ife0", "ife1", "ife2", "top";
> +
> + reg = <0x0 0x0acb3000 0x0 0x1000>,
> + <0x0 0x0acba000 0x0 0x1000>,
> + <0x0 0x0acc1000 0x0 0x1000>,
Alignment did not improve. Please carefully read DTS coding style.
> + <0x0 0x0acc8000 0x0 0x1000>,
> + <0x0 0x0accf000 0x0 0x1000>,
> + <0x0 0x0ace0000 0x0 0x2000>,
> + <0x0 0x0ace2000 0x0 0x2000>,
> + <0x0 0x0ace4000 0x0 0x2000>,
> + <0x0 0x0ace6000 0x0 0x2000>,
> + <0x0 0x0ace8000 0x0 0x2000>,
> + <0x0 0x0acaf000 0x0 0x4000>,
> + <0x0 0x0acb6000 0x0 0x4000>,
> + <0x0 0x0acbd000 0x0 0x4000>,
> + <0x0 0x0acc4000 0x0 0x4000>,
> + <0x0 0x0accb000 0x0 0x4000>;
> +
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
Alignment did not improve. Please carefully read DTS coding style.
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding
2024-10-11 14:49 ` Krzysztof Kozlowski
@ 2024-10-21 12:22 ` Vikram Sharma
0 siblings, 0 replies; 18+ messages in thread
From: Vikram Sharma @ 2024-10-21 12:22 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
Hi Krzysztof,
Thanks for your review. I will address the alignment issue as per DTS
coding style and will submit v4 for review.
Thanks,
Vikram
On 10/11/2024 8:19 PM, Krzysztof Kozlowski wrote:
> On Fri, Oct 11, 2024 at 07:39:25PM +0530, Vikram Sharma wrote:
>> @@ -0,0 +1,440 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +
> Drop blank line (that's a new finding, I would not complain except that
> I expect new version, see further).
>
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + camss: camss@acaf000 {
>> + compatible = "qcom,sc7280-camss";
>> +
>> + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
>> + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
>> + <&clock_camcc CAM_CC_IFE_2_CSID_CLK>,
>> + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
>> + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
>> + <&clock_camcc CAM_CC_CSIPHY0_CLK>,
>> + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
>> + <&clock_camcc CAM_CC_CSIPHY1_CLK>,
>> + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
>> + <&clock_camcc CAM_CC_CSIPHY2_CLK>,
>> + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
>> + <&clock_camcc CAM_CC_CSIPHY3_CLK>,
>> + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
>> + <&clock_camcc CAM_CC_CSIPHY4_CLK>,
>> + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>,
>> + <&gcc GCC_CAMERA_AHB_CLK>,
>> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
>> + <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
>> + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
>> + <&clock_camcc CAM_CC_IFE_0_CLK>,
>> + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
>> + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
>> + <&clock_camcc CAM_CC_IFE_1_CLK>,
>> + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
>> + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>,
>> + <&clock_camcc CAM_CC_IFE_2_CLK>,
>> + <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
>> + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>,
>> + <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
>> + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>,
>> + <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
>> +
>> + clock-names = "camnoc_axi",
>> + "csi0",
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + "csi1",
>> + "csi2",
>> + "csi3",
>> + "csi4",
>> + "csiphy0",
>> + "csiphy0_timer",
>> + "csiphy1",
>> + "csiphy1_timer",
>> + "csiphy2",
>> + "csiphy2_timer",
>> + "csiphy3",
>> + "csiphy3_timer",
>> + "csiphy4",
>> + "csiphy4_timer",
>> + "gcc_camera_ahb",
>> + "gcc_camera_axi",
>> + "soc_ahb",
>> + "vfe0_axi",
>> + "vfe0",
>> + "vfe0_cphy_rx",
>> + "vfe1_axi",
>> + "vfe1",
>> + "vfe1_cphy_rx",
>> + "vfe2_axi",
>> + "vfe2",
>> + "vfe2_cphy_rx",
>> + "vfe0_lite",
>> + "vfe0_lite_cphy_rx",
>> + "vfe1_lite",
>> + "vfe1_lite_cphy_rx";
>> +
>> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
>> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
> Alignment did not improve. Please carefully read DTS coding style.
>
>> +
>> + interconnect-names = "ahb", "hf_0";
>> +
>> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
>> +
>> + interrupt-names = "csid0",
>> + "csid1",
>> + "csid2",
>> + "csid_lite0",
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + "csid_lite1",
>> + "csiphy0",
>> + "csiphy1",
>> + "csiphy2",
>> + "csiphy3",
>> + "csiphy4",
>> + "vfe0",
>> + "vfe1",
>> + "vfe2",
>> + "vfe_lite0",
>> + "vfe_lite1";
>> +
>> + iommus = <&apps_smmu 0x800 0x4e0>;
>> +
>> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
>> + <&camcc CAM_CC_IFE_1_GDSC>,
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + <&camcc CAM_CC_IFE_2_GDSC>,
>> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
>> +
>> + power-domains-names = "ife0", "ife1", "ife2", "top";
>> +
>> + reg = <0x0 0x0acb3000 0x0 0x1000>,
>> + <0x0 0x0acba000 0x0 0x1000>,
>> + <0x0 0x0acc1000 0x0 0x1000>,
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + <0x0 0x0acc8000 0x0 0x1000>,
>> + <0x0 0x0accf000 0x0 0x1000>,
>> + <0x0 0x0ace0000 0x0 0x2000>,
>> + <0x0 0x0ace2000 0x0 0x2000>,
>> + <0x0 0x0ace4000 0x0 0x2000>,
>> + <0x0 0x0ace6000 0x0 0x2000>,
>> + <0x0 0x0ace8000 0x0 0x2000>,
>> + <0x0 0x0acaf000 0x0 0x4000>,
>> + <0x0 0x0acb6000 0x0 0x4000>,
>> + <0x0 0x0acbd000 0x0 0x4000>,
>> + <0x0 0x0acc4000 0x0 0x4000>,
>> + <0x0 0x0accb000 0x0 0x4000>;
>> +
>> + reg-names = "csid0",
>> + "csid1",
>> + "csid2",
>> + "csid_lite0",
> Alignment did not improve. Please carefully read DTS coding style.
>
>> + "csid_lite1",
>> + "csiphy0",
>> + "csiphy1",
>> + "csiphy2",
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:50 ` Krzysztof Kozlowski
2024-10-11 14:50 ` Krzysztof Kozlowski
2024-10-11 14:09 ` [PATCH v3 3/8] media: qcom: camss: Fix potential crash if domain attach fails Vikram Sharma
` (5 subsequent siblings)
7 siblings, 2 replies; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
The qcs6490-rb3gen2-vision-mezzanine is a mezz on top of the
qcs6490-rb3gen2 core kit. The vision mezzanine includes the
IMX577 camera sensor.
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 5de6290cd063..f00851f30d3e 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -390,6 +390,7 @@ properties:
- fairphone,fp5
- qcom,qcm6490-idp
- qcom,qcs6490-rb3gen2
+ - qcom,qcs6490-rb3gen2-vision-mezzanine
- shift,otter
- const: qcom,qcm6490
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine
2024-10-11 14:09 ` [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine Vikram Sharma
@ 2024-10-11 14:50 ` Krzysztof Kozlowski
2024-10-11 15:25 ` Bryan O'Donoghue
2024-10-11 14:50 ` Krzysztof Kozlowski
1 sibling, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-11 14:50 UTC (permalink / raw)
To: Vikram Sharma
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Fri, Oct 11, 2024 at 07:39:26PM +0530, Vikram Sharma wrote:
> The qcs6490-rb3gen2-vision-mezzanine is a mezz on top of the
> qcs6490-rb3gen2 core kit. The vision mezzanine includes the
> IMX577 camera sensor.
>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 5de6290cd063..f00851f30d3e 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -390,6 +390,7 @@ properties:
> - fairphone,fp5
> - qcom,qcm6490-idp
> - qcom,qcs6490-rb3gen2
> + - qcom,qcs6490-rb3gen2-vision-mezzanine
Shouldn't this be an overlay?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine
2024-10-11 14:50 ` Krzysztof Kozlowski
@ 2024-10-11 15:25 ` Bryan O'Donoghue
2024-10-11 21:33 ` Dmitry Baryshkov
0 siblings, 1 reply; 18+ messages in thread
From: Bryan O'Donoghue @ 2024-10-11 15:25 UTC (permalink / raw)
To: Krzysztof Kozlowski, Vikram Sharma
Cc: rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, akapatra,
hariramp, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will, linux-arm-kernel,
linux-media, linux-arm-msm, devicetree, linux-kernel, kernel
On 11/10/2024 15:50, Krzysztof Kozlowski wrote:
> On Fri, Oct 11, 2024 at 07:39:26PM +0530, Vikram Sharma wrote:
>> The qcs6490-rb3gen2-vision-mezzanine is a mezz on top of the
>> qcs6490-rb3gen2 core kit. The vision mezzanine includes the
>> IMX577 camera sensor.
>>
>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 5de6290cd063..f00851f30d3e 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -390,6 +390,7 @@ properties:
>> - fairphone,fp5
>> - qcom,qcm6490-idp
>> - qcom,qcs6490-rb3gen2
>> + - qcom,qcs6490-rb3gen2-vision-mezzanine
>
> Shouldn't this be an overlay?
>
> Best regards,
> Krzysztof
>
Because of broken bootloaders which don't do overlays, we've been adding
additional dts instead.
For preference everybody would run u-boot, grub or another reasonable
bootloader that can apply an overlay.
Last time I checked there was no support for dtbo upstream in the kernel
itself.
greps
grep -r of_overlay_fdt_apply *
Hmm, does this do what I think it does ? Its news to me if there's a way
to do this in the kernel now TBH.
Otherwise the sad situation with shipping bootloaders means we are
pretty much stuck with the one blob which we can't apply an update to.
---
bod
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine
2024-10-11 15:25 ` Bryan O'Donoghue
@ 2024-10-11 21:33 ` Dmitry Baryshkov
2024-10-11 22:31 ` Bryan O'Donoghue
0 siblings, 1 reply; 18+ messages in thread
From: Dmitry Baryshkov @ 2024-10-11 21:33 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: Krzysztof Kozlowski, Vikram Sharma, rfoss, todor.too, mchehab,
robh, krzk+dt, conor+dt, akapatra, hariramp, andersson,
konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will, linux-arm-kernel, linux-media,
linux-arm-msm, devicetree, linux-kernel, kernel
On Fri, Oct 11, 2024 at 04:25:15PM +0100, Bryan O'Donoghue wrote:
> On 11/10/2024 15:50, Krzysztof Kozlowski wrote:
> > On Fri, Oct 11, 2024 at 07:39:26PM +0530, Vikram Sharma wrote:
> > > The qcs6490-rb3gen2-vision-mezzanine is a mezz on top of the
> > > qcs6490-rb3gen2 core kit. The vision mezzanine includes the
> > > IMX577 camera sensor.
> > >
> > > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> > > ---
> > > Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> > > index 5de6290cd063..f00851f30d3e 100644
> > > --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> > > @@ -390,6 +390,7 @@ properties:
> > > - fairphone,fp5
> > > - qcom,qcm6490-idp
> > > - qcom,qcs6490-rb3gen2
> > > + - qcom,qcs6490-rb3gen2-vision-mezzanine
> >
> > Shouldn't this be an overlay?
> >
> > Best regards,
> > Krzysztof
> >
>
> Because of broken bootloaders which don't do overlays, we've been adding
> additional dts instead.
>
> For preference everybody would run u-boot, grub or another reasonable
> bootloader that can apply an overlay.
>
> Last time I checked there was no support for dtbo upstream in the kernel
> itself.
See arch/arm64/boot/dts/qcom/Makefile:
sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
>
> greps
>
> grep -r of_overlay_fdt_apply *
>
> Hmm, does this do what I think it does ? Its news to me if there's a way to
> do this in the kernel now TBH.
>
> Otherwise the sad situation with shipping bootloaders means we are pretty
> much stuck with the one blob which we can't apply an update to.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine
2024-10-11 21:33 ` Dmitry Baryshkov
@ 2024-10-11 22:31 ` Bryan O'Donoghue
0 siblings, 0 replies; 18+ messages in thread
From: Bryan O'Donoghue @ 2024-10-11 22:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Vikram Sharma, rfoss, todor.too, mchehab,
robh, krzk+dt, conor+dt, akapatra, hariramp, andersson,
konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will, linux-arm-kernel, linux-media,
linux-arm-msm, devicetree, linux-kernel, kernel
On 11/10/2024 22:33, Dmitry Baryshkov wrote:
> See arch/arm64/boot/dts/qcom/Makefile:
>
> sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo
>
> dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
Aha, yes ok _that_ makes sense to me.
---
bod
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine
2024-10-11 14:09 ` [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine Vikram Sharma
2024-10-11 14:50 ` Krzysztof Kozlowski
@ 2024-10-11 14:50 ` Krzysztof Kozlowski
1 sibling, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-11 14:50 UTC (permalink / raw)
To: Vikram Sharma
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Fri, Oct 11, 2024 at 07:39:26PM +0530, Vikram Sharma wrote:
> The qcs6490-rb3gen2-vision-mezzanine is a mezz on top of the
> qcs6490-rb3gen2 core kit. The vision mezzanine includes the
> IMX577 camera sensor.
>
Please use subject prefixes matching the subsystem. You can get them for
example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 3/8] media: qcom: camss: Fix potential crash if domain attach fails
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 4/8] media: qcom: camss: Sort CAMSS version enums and compatible strings Vikram Sharma
` (4 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel, stable
Fix a potential crash in camss by ensuring detach is skipped if attach
is unsuccessful.
Fixes: d89751c61279 ("media: qcom: camss: Add support for named power-domains")
CC: stable@vger.kernel.org
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
drivers/media/platform/qcom/camss/camss.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index d64985ca6e88..b6658df37709 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2131,8 +2131,7 @@ static int camss_configure_pd(struct camss *camss)
camss->genpd = dev_pm_domain_attach_by_name(camss->dev,
camss->res->pd_name);
if (IS_ERR(camss->genpd)) {
- ret = PTR_ERR(camss->genpd);
- goto fail_pm;
+ return PTR_ERR(camss->genpd);
}
}
@@ -2149,7 +2148,7 @@ static int camss_configure_pd(struct camss *camss)
ret = -ENODEV;
else
ret = PTR_ERR(camss->genpd);
- goto fail_pm;
+ return ret;
}
camss->genpd_link = device_link_add(camss->dev, camss->genpd,
DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 4/8] media: qcom: camss: Sort CAMSS version enums and compatible strings
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
` (2 preceding siblings ...)
2024-10-11 14:09 ` [PATCH v3 3/8] media: qcom: camss: Fix potential crash if domain attach fails Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 5/8] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma
` (3 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Sort CAMSS version enums and compatible strings alphanumerically.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 10 +++++-----
drivers/media/platform/qcom/camss/camss-vfe.c | 6 +++---
drivers/media/platform/qcom/camss/camss.c | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index df7e93a5a4f6..7d2490c9de01 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -505,10 +505,6 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
u32 val;
switch (csiphy->camss->res->version) {
- case CAMSS_845:
- r = &lane_regs_sdm845[0][0];
- array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
- break;
case CAMSS_8250:
r = &lane_regs_sm8250[0][0];
array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
@@ -517,6 +513,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
r = &lane_regs_sc8280xp[0][0];
array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]);
break;
+ case CAMSS_845:
+ r = &lane_regs_sdm845[0][0];
+ array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
+ break;
default:
WARN(1, "unknown cspi version\n");
return;
@@ -557,9 +557,9 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
- case CAMSS_845:
case CAMSS_8250:
case CAMSS_8280XP:
+ case CAMSS_845:
ret = true;
break;
}
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 83c5a36d071f..ffcb1e2ec417 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -333,11 +333,11 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
return sink_code;
}
break;
- case CAMSS_8x96:
case CAMSS_660:
- case CAMSS_845:
+ case CAMSS_8x96:
case CAMSS_8250:
case CAMSS_8280XP:
+ case CAMSS_845:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
{
@@ -1692,9 +1692,9 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
- case CAMSS_845:
case CAMSS_8250:
case CAMSS_8280XP:
+ case CAMSS_845:
ret = 16;
break;
default:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index b6658df37709..dfa0213ecfbf 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2446,10 +2446,10 @@ static const struct camss_resources sc8280xp_resources = {
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
- { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 5/8] media: qcom: camss: Add support for camss driver on SC7280
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
` (3 preceding siblings ...)
2024-10-11 14:09 ` [PATCH v3 4/8] media: qcom: camss: Sort CAMSS version enums and compatible strings Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 6/8] media: qcom: camss: Restructure camss_link_entities Vikram Sharma
` (2 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
From: Suresh Vankadara <quic_svankada@quicinc.com>
Add support for the camss driver on the SC7280 SoC.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../media/platform/qcom/camss/camss-csid.c | 1 -
.../qcom/camss/camss-csiphy-3ph-1-0.c | 5 +
.../media/platform/qcom/camss/camss-csiphy.c | 5 +
.../media/platform/qcom/camss/camss-csiphy.h | 1 +
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 339 ++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
7 files changed, 353 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 858db5d4ca75..8d3dc26e2af4 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -1028,7 +1028,6 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid,
csid->res->hw_ops->subdev_init(csid);
/* Memory */
-
if (camss->res->version == CAMSS_8250) {
/* for titan 480, CSID registers are inside the VFE region,
* between the VFE "top" and "bus" registers. this requires
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 7d2490c9de01..f341f7b7fd8a 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
u32 val;
switch (csiphy->camss->res->version) {
+ case CAMSS_7280:
+ r = &lane_regs_sm8250[0][0];
+ array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
+ break;
case CAMSS_8250:
r = &lane_regs_sm8250[0][0];
array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
@@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
+ case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index 2f7361dfd461..b3525ad81ffd 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -108,6 +108,11 @@ const struct csiphy_formats csiphy_formats_sdm845 = {
.formats = formats_sdm845
};
+const struct csiphy_formats csiphy_formats_sc7280 = {
+ .nformats = ARRAY_SIZE(formats_sdm845),
+ .formats = formats_sdm845
+};
+
/*
* csiphy_get_bpp - map media bus format to bits per pixel
* @formats: supported media bus formats array
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index 47f0b6b09eba..9295f2fc6745 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -110,6 +110,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
extern const struct csiphy_formats csiphy_formats_8x16;
extern const struct csiphy_formats csiphy_formats_8x96;
extern const struct csiphy_formats csiphy_formats_sdm845;
+extern const struct csiphy_formats csiphy_formats_sc7280;
extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index ffcb1e2ec417..61f6815a3756 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -334,6 +334,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
}
break;
case CAMSS_660:
+ case CAMSS_7280:
case CAMSS_8x96:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -1692,6 +1693,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
+ case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index dfa0213ecfbf..7ae4a1312e9f 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -1480,6 +1480,330 @@ static const struct resources_icc icc_res_sc8280xp[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_7280[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {},
+ .clock = { "csiphy0", "csiphy0_timer"},
+ .clock_rate = {
+ { 300000000 },
+ { 300000000 }
+ },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {},
+ .clock = { "csiphy1", "csiphy1_timer"},
+ .clock_rate = {
+ { 300000000 },
+ { 300000000 }
+ },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {},
+ .clock = { "csiphy2", "csiphy2_timer"},
+ .clock_rate = {
+ { 300000000 },
+ { 300000000 }
+ },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = {},
+ .clock = { "csiphy3", "csiphy3_timer"},
+ .clock_rate = {
+ { 300000000 },
+ { 300000000 }
+ },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = {},
+ .clock = { "csiphy4", "csiphy4_timer"},
+ .clock_rate = {
+ { 300000000 },
+ { 300000000 }
+ },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_7280[] = {
+ /* CSID0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csi0", "vfe0_cphy_rx", "vfe0", "soc_ahb"},
+ .clock_rate = {
+ { 300000000, 0, 380000000, 0},
+ { 400000000, 0, 510000000, 0},
+ { 400000000, 0, 637000000, 0},
+ { 400000000, 0, 760000000, 0}
+ },
+
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csi1", "vfe1_cphy_rx", "vfe1", "soc_ahb"},
+ .clock_rate = {
+ { 300000000, 0, 380000000, 0},
+ { 400000000, 0, 510000000, 0},
+ { 400000000, 0, 637000000, 0},
+ { 400000000, 0, 760000000, 0}
+ },
+
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csi2", "vfe2_cphy_rx", "vfe2", "soc_ahb"},
+ .clock_rate = {
+ { 300000000, 0, 380000000, 0},
+ { 400000000, 0, 510000000, 0},
+ { 400000000, 0, 637000000, 0},
+ { 400000000, 0, 760000000, 0}
+ },
+
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID3 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"},
+ .clock_rate = {
+ { 300000000, 0, 320000000, 0},
+ { 400000000, 0, 400000000, 0},
+ { 400000000, 0, 480000000, 0},
+ { 400000000, 0, 600000000, 0}
+ },
+
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID4 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"},
+ .clock_rate = {
+ { 300000000, 0, 320000000, 0},
+ { 400000000, 0, 400000000, 0},
+ { 400000000, 0, 480000000, 0},
+ { 400000000, 0, 600000000, 0}
+ },
+
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_7280[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe0", "vfe0_axi", "soc_ahb",
+ "camnoc_axi", "gcc_camera_axi"},
+ .clock_rate = {
+ { 380000000, 0, 80000000, 150000000, 0},
+ { 510000000, 0, 80000000, 240000000, 0},
+ { 637000000, 0, 80000000, 320000000, 0},
+ { 760000000, 0, 80000000, 400000000, 0},
+ { 760000000, 0, 80000000, 480000000, 0},
+ },
+
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe1", "vfe1_axi", "soc_ahb",
+ "camnoc_axi", "gcc_camera_axi"},
+ .clock_rate = {
+ { 380000000, 0, 80000000, 150000000, 0},
+ { 510000000, 0, 80000000, 240000000, 0},
+ { 637000000, 0, 80000000, 320000000, 0},
+ { 760000000, 0, 80000000, 400000000, 0},
+ { 760000000, 0, 80000000, 480000000, 0},
+ },
+
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe2", "vfe2_axi", "soc_ahb",
+ "camnoc_axi", "gcc_camera_axi"},
+ .clock_rate = {
+ { 380000000, 0, 80000000, 150000000, 0},
+ { 510000000, 0, 80000000, 240000000, 0},
+ { 637000000, 0, 80000000, 320000000, 0},
+ { 760000000, 0, 80000000, 400000000, 0},
+ { 760000000, 0, 80000000, 480000000, 0},
+ },
+
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .hw_ops = &vfe_ops_170,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 (lite) */
+ {
+ .clock = { "vfe0_lite", "soc_ahb",
+ "camnoc_axi", "gcc_camera_axi"},
+ .clock_rate = {
+ { 320000000, 80000000, 150000000, 0},
+ { 400000000, 80000000, 240000000, 0},
+ { 480000000, 80000000, 320000000, 0},
+ { 600000000, 80000000, 400000000, 0},
+ },
+
+ .regulators = {},
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 (lite) */
+ {
+ .clock = { "vfe1_lite", "soc_ahb",
+ "camnoc_axi", "gcc_camera_axi"},
+ .clock_rate = {
+ { 320000000, 80000000, 150000000, 0},
+ { 400000000, 80000000, 240000000, 0},
+ { 480000000, 80000000, 320000000, 0},
+ { 600000000, 80000000, 400000000, 0},
+ },
+
+ .regulators = {},
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_sc7280[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_0",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
/*
* camss_add_clock_margin - Add margin to clock frequency rate
* @rate: Clock frequency rate
@@ -2443,9 +2767,24 @@ static const struct camss_resources sc8280xp_resources = {
.link_entities = camss_link_entities
};
+static const struct camss_resources sc7280_resources = {
+ .version = CAMSS_7280,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_7280,
+ .csid_res = csid_res_7280,
+ .vfe_res = vfe_res_7280,
+ .icc_res = icc_res_sc7280,
+ .icc_path_num = ARRAY_SIZE(icc_res_sc7280),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_7280),
+ .csid_num = ARRAY_SIZE(csid_res_7280),
+ .vfe_num = ARRAY_SIZE(vfe_res_7280),
+ .link_entities = camss_link_entities
+};
+
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 73c47c07fc30..16e527f8b831 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -76,6 +76,7 @@ enum camss_version {
CAMSS_8x16,
CAMSS_8x96,
CAMSS_660,
+ CAMSS_7280,
CAMSS_845,
CAMSS_8250,
CAMSS_8280XP,
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 6/8] media: qcom: camss: Restructure camss_link_entities
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
` (4 preceding siblings ...)
2024-10-11 14:09 ` [PATCH v3 5/8] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 7/8] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
2024-10-11 14:09 ` [PATCH v3 8/8] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
7 siblings, 0 replies; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Refactor the camss_link_entities function by breaking it down into
three distinct functions. Each function will handle the linking of
a specific entity separately, enhancing readability.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
drivers/media/platform/qcom/camss/camss.c | 159 ++++++++++++++--------
1 file changed, 105 insertions(+), 54 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 7ae4a1312e9f..db2710ad0d5c 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2152,14 +2152,66 @@ static int camss_init_subdevices(struct camss *camss)
}
/*
- * camss_link_entities - Register subdev nodes and create links
+ * camss_link_entities_csid - Register subdev nodes and create links
* @camss: CAMSS device
*
* Return 0 on success or a negative error code on failure
*/
-static int camss_link_entities(struct camss *camss)
+static int camss_link_entities_csid(struct camss *camss)
{
- int i, j, k;
+ int i, j;
+ int ret, line_num;
+ u16 src_pad;
+ u16 sink_pad;
+ struct media_entity *src_entity;
+ struct media_entity *sink_entity;
+
+ for (i = 0; i < camss->res->csid_num; i++) {
+ if (camss->ispif)
+ line_num = camss->ispif->line_num;
+ else
+ line_num = camss->vfe[i].res->line_num;
+
+ src_entity = &camss->csid[i].subdev.entity;
+ for (j = 0; j < line_num; j++) {
+ if (camss->ispif) {
+ sink_entity = &camss->ispif->line[j].subdev.entity;
+ src_pad = MSM_CSID_PAD_SRC;
+ sink_pad = MSM_ISPIF_PAD_SINK;
+ } else {
+ sink_entity = &camss->vfe[i].line[j].subdev.entity;
+ src_pad = MSM_CSID_PAD_FIRST_SRC + j;
+ sink_pad = MSM_VFE_PAD_SINK;
+ }
+
+ ret = media_create_pad_link(src_entity,
+ src_pad,
+ sink_entity,
+ sink_pad,
+ 0);
+ if (ret < 0) {
+ dev_err(camss->dev,
+ "Failed to link %s->%s entities: %d\n",
+ src_entity->name,
+ sink_entity->name,
+ ret);
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * camss_link_entities_csiphy - Register subdev nodes and create links
+ * @camss: CAMSS device
+ *
+ * Return 0 on success or a negative error code on failure
+ */
+static int camss_link_entities_csiphy(struct camss *camss)
+{
+ int i, j;
int ret;
for (i = 0; i < camss->res->csiphy_num; i++) {
@@ -2180,71 +2232,70 @@ static int camss_link_entities(struct camss *camss)
}
}
- if (camss->ispif) {
- for (i = 0; i < camss->res->csid_num; i++) {
- for (j = 0; j < camss->ispif->line_num; j++) {
- ret = media_create_pad_link(&camss->csid[i].subdev.entity,
- MSM_CSID_PAD_SRC,
- &camss->ispif->line[j].subdev.entity,
- MSM_ISPIF_PAD_SINK,
+ return 0;
+}
+
+/*
+ * camss_link_entities_ispif - Register subdev nodes and create links
+ * @camss: CAMSS device
+ *
+ * Return 0 on success or a negative error code on failure
+ */
+static int camss_link_entities_ispif(struct camss *camss)
+{
+ int i, j, k;
+ int ret;
+
+ for (i = 0; i < camss->ispif->line_num; i++) {
+ for (k = 0; k < camss->res->vfe_num; k++) {
+ for (j = 0; j < camss->vfe[k].res->line_num; j++) {
+ struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
+ struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
+
+ ret = media_create_pad_link(&ispif->entity,
+ MSM_ISPIF_PAD_SRC,
+ &vfe->entity,
+ MSM_VFE_PAD_SINK,
0);
if (ret < 0) {
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
- camss->csid[i].subdev.entity.name,
- camss->ispif->line[j].subdev.entity.name,
+ ispif->entity.name,
+ vfe->entity.name,
ret);
return ret;
}
}
}
-
- for (i = 0; i < camss->ispif->line_num; i++)
- for (k = 0; k < camss->res->vfe_num; k++)
- for (j = 0; j < camss->vfe[k].res->line_num; j++) {
- struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
- struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
-
- ret = media_create_pad_link(&ispif->entity,
- MSM_ISPIF_PAD_SRC,
- &vfe->entity,
- MSM_VFE_PAD_SINK,
- 0);
- if (ret < 0) {
- dev_err(camss->dev,
- "Failed to link %s->%s entities: %d\n",
- ispif->entity.name,
- vfe->entity.name,
- ret);
- return ret;
- }
- }
- } else {
- for (i = 0; i < camss->res->csid_num; i++)
- for (k = 0; k < camss->res->vfe_num; k++)
- for (j = 0; j < camss->vfe[k].res->line_num; j++) {
- struct v4l2_subdev *csid = &camss->csid[i].subdev;
- struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
-
- ret = media_create_pad_link(&csid->entity,
- MSM_CSID_PAD_FIRST_SRC + j,
- &vfe->entity,
- MSM_VFE_PAD_SINK,
- 0);
- if (ret < 0) {
- dev_err(camss->dev,
- "Failed to link %s->%s entities: %d\n",
- csid->entity.name,
- vfe->entity.name,
- ret);
- return ret;
- }
- }
}
return 0;
}
+/*
+ * camss_link_entities - Register subdev nodes and create links
+ * @camss: CAMSS device
+ *
+ * Return 0 on success or a negative error code on failure
+ */
+static int camss_link_entities(struct camss *camss)
+{
+ int ret;
+
+ ret = camss_link_entities_csiphy(camss);
+ if (ret < 0)
+ return ret;
+
+ ret = camss_link_entities_csid(camss);
+ if (ret < 0)
+ return ret;
+
+ if (camss->ispif)
+ ret = camss_link_entities_ispif(camss);
+
+ return ret;
+}
+
/*
* camss_register_entities - Register subdev nodes and create links
* @camss: CAMSS device
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 7/8] arm64: dts: qcom: sc7280: Add support for camss
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
` (5 preceding siblings ...)
2024-10-11 14:09 ` [PATCH v3 6/8] media: qcom: camss: Restructure camss_link_entities Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:51 ` Krzysztof Kozlowski
2024-10-11 14:09 ` [PATCH v3 8/8] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
7 siblings, 1 reply; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Add changes to support the camera subsystem on the SC7280.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 175 +++++++++++++++++++++++++++
1 file changed, 175 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b41230651def..9bab2d8dc1b4 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4426,6 +4426,181 @@ cci1_i2c1: i2c-bus@1 {
};
};
+ camss: camss@acaf000 {
+ compatible = "qcom,sc7280-camss";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_2_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_2_AXI_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
+
+ clock-names = "camnoc_axi",
+ "csi0",
+ "csi1",
+ "csi2",
+ "csi3",
+ "csi4",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_camera_ahb",
+ "gcc_camera_axi",
+ "soc_ahb",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe2_axi",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe0_lite",
+ "vfe0_lite_cphy_rx",
+ "vfe1_lite",
+ "vfe1_lite_cphy_rx";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
+
+ interconnect-names = "ahb", "hf_0";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ iommus = <&apps_smmu 0x800 0x4e0>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ power-domains-names = "ife0", "ife1", "ife2", "top";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc1000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0accf000 0x0 0x1000>,
+ <0x0 0x0ace0000 0x0 0x2000>,
+ <0x0 0x0ace2000 0x0 0x2000>,
+ <0x0 0x0ace4000 0x0 0x2000>,
+ <0x0 0x0ace6000 0x0 0x2000>,
+ <0x0 0x0ace8000 0x0 0x2000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acbd000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0accb000 0x0 0x4000>;
+
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0 0x0ad00000 0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v3 7/8] arm64: dts: qcom: sc7280: Add support for camss
2024-10-11 14:09 ` [PATCH v3 7/8] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
@ 2024-10-11 14:51 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-11 14:51 UTC (permalink / raw)
To: Vikram Sharma
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Fri, Oct 11, 2024 at 07:39:31PM +0530, Vikram Sharma wrote:
> Add changes to support the camera subsystem on the SC7280.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 175 +++++++++++++++++++++++++++
> 1 file changed, 175 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index b41230651def..9bab2d8dc1b4 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -4426,6 +4426,181 @@ cci1_i2c1: i2c-bus@1 {
> };
> };
>
> + camss: camss@acaf000 {
> + compatible = "qcom,sc7280-camss";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_2_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_2_AXI_CLK>,
> + <&camcc CAM_CC_IFE_2_CLK>,
> + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
> +
> + clock-names = "camnoc_axi",
> + "csi0",
> + "csi1",
Everything misaligned here as well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 8/8] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine
2024-10-11 14:09 [PATCH v3 0/8] media: qcom: camss: Add sc7280 support Vikram Sharma
` (6 preceding siblings ...)
2024-10-11 14:09 ` [PATCH v3 7/8] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
@ 2024-10-11 14:09 ` Vikram Sharma
2024-10-11 14:52 ` Krzysztof Kozlowski
7 siblings, 1 reply; 18+ messages in thread
From: Vikram Sharma @ 2024-10-11 14:09 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
The Vision Mezzanine for the RB3 ships with an imx577 camera sensor.
Enable the IMX577 on the vision mezzanine.
An example media-ctl pipeline for the imx577 is:
media-ctl --reset
media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]'
media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0
Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../qcom/qcs6490-rb3gen2-vision-mezzanine.dts | 61 +++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 33 ++++++++++
3 files changed, 95 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index aea1d69db541..7208da1d3697 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -111,6 +111,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts
new file mode 100644
index 000000000000..04b5fe80d38d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "qcs6490-rb3gen2.dts"
+
+&camcc {
+ status = "okay";
+};
+
+&camss {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+
+ ports {
+ /* The port index denotes CSIPHY id i.e. csiphy3 */
+ port@3 {
+ reg = <3>;
+ csiphy3_ep: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&imx577_ep>;
+ };
+ };
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c1 {
+ camera@1a {
+ compatible = "sony,imx577";
+ reg = <0x1a>;
+
+ reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "suspend";
+ pinctrl-0 = <&cam2_default>;
+ pinctrl-1 = <&cam2_suspend>;
+
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ dovdd-supply = <&vreg_l18b_1p8>;
+
+ port {
+ imx577_ep: endpoint {
+ clock-lanes = <7>;
+ link-frequencies = /bits/ 64 <600000000>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy3_ep>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 9bab2d8dc1b4..74f65129e653 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5115,6 +5115,39 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ cam2_default: cam2-default-state {
+ rst-pins {
+ pins = "gpio78";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk-pins {
+ pins = "gpio67";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cam2_suspend: cam2-suspend-state {
+ rst-pins {
+ pins = "gpio78";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+
+ mclk-pins {
+ pins = "gpio67";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
cci0_default: cci0-default-state {
pins = "gpio69", "gpio70";
function = "cci_i2c";
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v3 8/8] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine
2024-10-11 14:09 ` [PATCH v3 8/8] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
@ 2024-10-11 14:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-11 14:52 UTC (permalink / raw)
To: Vikram Sharma
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Fri, Oct 11, 2024 at 07:39:32PM +0530, Vikram Sharma wrote:
> The Vision Mezzanine for the RB3 ships with an imx577 camera sensor.
> Enable the IMX577 on the vision mezzanine.
>
> An example media-ctl pipeline for the imx577 is:
>
> media-ctl --reset
> media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]'
> media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]'
> media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
> media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
> media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]'
> media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
>
> yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0
>
> Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../qcom/qcs6490-rb3gen2-vision-mezzanine.dts | 61 +++++++++++++++++++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 33 ++++++++++
> 3 files changed, 95 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index aea1d69db541..7208da1d3697 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -111,6 +111,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts
> new file mode 100644
> index 000000000000..04b5fe80d38d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "qcs6490-rb3gen2.dts"
DTS does not include DTS, but DTSI.
And where is the compatible you wanted to use? This looks sketchy...
mezzanines are supposed to be overlays, I think.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread