From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F08768BEF; Wed, 26 Jun 2024 09:41:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719394901; cv=none; b=JwepR0FuLlI550LZ9HYE4cHtQbPTfb2d7/xS+w+Iyqpn5vvFxf19oUVHlKc/647pL/Z0TQyADNXceYroNnxeXG3F0UKfjwQxusw36/2XuSDnMyxhmArFbLFAFAY3d+JxQBL94/MRXirzJdyV06LZw9KHdsWf6/OouLycsQS8WsE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719394901; c=relaxed/simple; bh=s3z7HXMv4Han+cJsdchl0Tjew+5XriJiwIN+Ja5UnaI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=MeNL21XRxpDXvNONeZ90HD7NY95wfBj4RXr2/vjID1LpA8GAXTJlKXRS9E1+a1rZJjsMVzRvdkBa/tnKEPbiRmmn3GJx/+8cJHM4kwP0Ad98XPxR4RU/3jkgwAKfEWbHFbyBMF+zqOpvxiUDWcmD/fYvZOTa0R25lOxfR/api7M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uOrrSKWm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uOrrSKWm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C58D4C32786; Wed, 26 Jun 2024 09:41:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719394900; bh=s3z7HXMv4Han+cJsdchl0Tjew+5XriJiwIN+Ja5UnaI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=uOrrSKWmRIW4TSdz+ruUE1K5qfT30Xcy9B4W9WAYRPr0ClteEew+XD0o8YxxRtYHj d9412DC9EwkSRtEYo+rYXmmhw26ome1CIq5U/zB3CKH8k3tvIjRcyjEK00INVhPii/ XCcMXIUU9HuxGhokj4CDpQixmu9xU7xSBiqRuGIpS30+fD9B8/iU4LxX9iN005G2xh Gf5Mthm42iLQgZAMPHmOicHnjyipeVIGIDzk2VX6/PfZvm38n1rEoywuSZRV4PKFy2 TK3qFxAaK9TsN+pxFNl9leYVXXvNSJRD5yYG3+JbhFl5nwAy3miz/mv7jYnsDvfQGY d0CrnQq6a+LnQ== Message-ID: <214be4bb-3e24-4868-8cb7-db73b6cd4b50@kernel.org> Date: Wed, 26 Jun 2024 11:41:33 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG To: Geert Uytterhoeven Cc: "Lad, Prabhakar" , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Lad Prabhakar References: <20240610233221.242749-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240610233221.242749-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <34b21e6f-0896-4691-9b66-d06ef2f44905@kernel.org> <20438973-d7a1-427f-a2ed-5c5b9f7db872@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 26/06/2024 11:35, Geert Uytterhoeven wrote: > Hi Krzysztof, > > On Thu, Jun 13, 2024 at 2:57 PM Krzysztof Kozlowski wrote: >> On 13/06/2024 11:53, Lad, Prabhakar wrote: >>> On Tue, Jun 11, 2024 at 8:02 AM Krzysztof Kozlowski wrote: >>>> On 11/06/2024 01:32, Prabhakar wrote: >>>>> From: Lad Prabhakar >>>>> >>>>> Document the device tree bindings for the Renesas RZ/V2H(P) SoC >>>>> Clock Pulse Generator (CPG). >>>>> >>>>> CPG block handles the below operations: >>>>> - Generation and control of clock signals for the IP modules >>>>> - Generation and control of resets >>>>> - Control over booting >>>>> - Low power consumption and power supply domains >>>>> >>>>> Signed-off-by: Lad Prabhakar > >>>>> + '#clock-cells': >>>>> + description: | >>>>> + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" >>>>> + and a core clock reference, as defined in >>>>> + , >>>> >>>> So second cell is not used? >>>> >>> It will be used for blocks using core clocks. >>> >>>>> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and >>>>> + a module number. The module number is calculated as the CLKON register >>>>> + offset index multiplied by 16, plus the actual bit in the register >>>>> + used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the >>>>> + calculation is (1 * 16 + 3) = 19. >>>> >>>> You should not have different values. Make it const: 1 and just use IDs. >>>> >>> Are you suggesting not to differentiate between core/mod clocks. They >>> are differentiated because the MOD clocks can turned ON/OFF but where >>> as with the core clocks we cannot turn them ON/OF so the driver needs >>> to know this, hence two specifiers are used. >> >> Every driver knows it... I am really, what is the problem here? Are you >> saying the drivers create some unknown clocks? > > The driver knows for sure which clocks are module clocks, and thus can > be used for power management. To simplify the driver, two separate > numbers spaces are used: > 1. Core clock numbers come from IDs in the DT binding headers, > 2. Module clock numbers come straight[1] from the hardware docs. > As the latter are fixed, merging them into a single number space in > a future-proof way is hard[2], the bindings use 2 clock cells. IIUC, your module clock numbers are not DT ABI and should not be put into the binding headers. I think that's the case currently, right? If above is correct, considering your explanation I am fine. Thanks for the time to make it clear. > > Alternatively, a unified number space using IDs in the DT binding > headers could be used, as you suggest. > > [1] "straight" may be a misnomer here, as the DT writer still has to > calculate the number from register index and bit index: > > n = register index * 16 + bit index > > i.e. register index 1 and register bit 3 become 19. > > In the R-Car series, this is handled slightly more elegant > (IMHO ;-), and easier to the human eye, by using a sparse > number space: > > n = register index * 100 + bit index > > i.e. register index 1 and register bit 3 become 103. > Which also matches how the bits were named in older SH-Mobile > hardware docs. > > [2] One could use an offset to indicate core or module clocks, but > future SoCs in the family may have more clocks. > Best regards, Krzysztof