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From: Arnd Bergmann <arnd@arndb.de>
To: cw00.choi@samsung.com
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>,
	"linux-samsung-soc@vger.kernel.org"
	<linux-samsung-soc@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"kgene.kim@samsung.com" <kgene.kim@samsung.com>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"olof@lixom.net" <olof@lixom.net>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	"tomasz.figa@gmail.com" <tomasz.figa@gmail.com>,
	"thomas.abraham@linaro.org" <thomas.abraham@linaro.org>,
	"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
	"kyungmin.park@samsung.com" <kyungmin.park@samsung.com>,
	"inki.dae@samsung.com" <inki.dae@samsung.com>,
	"chanho61.park@samsung.com" <chanho61.park@samsung.com>,
	"geunsik.lim@samsung.com" <geunsik.lim@samsung.com>,
	"sw0312.kim@samsung.com" <sw0312.kim@samsung.com>,
	"jh80.chung@samsung.com" <jh80.chung@samsu>
Subject: Re: [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
Date: Thu, 27 Nov 2014 16:33:26 +0100	[thread overview]
Message-ID: <2150099.t3m9xROUE3@wuerfel> (raw)
In-Reply-To: <CAGTfZH1DdBGYKXv6VgWYfqfcyWVMm8MLux1U7sn_rX5h3-TGNQ@mail.gmail.com>

On Friday 28 November 2014 00:17:40 Chanwoo Choi wrote:
> 
> But, "fixed-clock" pass all properties from dt file to
> driver/clk/clk-fixed-rate.c.
> and "fixed-clock" driver has not the data dependent on h/w. e.g.,
> clock offset, parent clock.

The parent clocks would obviously have to be provided in DT if you
do this. I'm not sure what you mean with clock offsets. What would
it take to describe that?

> >> >
> >> > > >     clock-controller@113600000 {
> >> > > >             reg = <0 0x113600000 0 0x1000>;
> >> > > >             compatible = "samsung,exynos5433-cmu";
> >> > > >             #clock-cells = <1>;
> >> > > >     };
> >> > > >
> >> > > >     clock-controller@114800000 {
> >> > > >             reg = <0 0x114800000 0 0x1000>;
> >> > > >             compatible = "samsung,exynos5433-cmu";
> >> > > >             #clock-cells = <1>;
> >> > > >     };
> >> > > >
> >> > > > The code will just map the local registers for each instance and then
> >> > > > provide the clocks of the right instance when asked for it.
> >> > >
> >> > > Each clock domain has not the same mux/divider/clock. So, just one
> >> > compatible
> >> > > string could not support all of clock domains.
> >> >
> >> > What are the specific differences?
> >>
> >>
> >>
> >> > I'm not sure that difference among clock domains because I think it is
> >> dependent on the opinion of architect of SoC.
> >>
> >> cmu_bus0/1/2 are much similar. Just cmu_bus2 has one more mux/gate clock
> >> than cmu_bus0/1.
> >
> > Yes, that's what I mean. You can simply model that extra mux/gate
> > in the driver, as long as nothing ever tries to access the clock.
> 
> If only use one compatible to support CMU_BUSx domains,
> I would implement it as following with Sylwester's guide.
> 
> To Sylwester, Tomaz,
> Are you agree following method to support CMU_BUSx domains
> by using one compatible string?


> +#define bus_clk_regs(num)                \
> +static unsigned long bus##num_clk_regs[] __initdata = {    \
> +    DIV_BUS,                    \
> +    DIV_STAT_BUS,                    \
> +    ENABLE_ACLK_BUS,                \
> +    ENABLE_PCLK_BUS,                \
> +    ENABLE_IP_BUS0,                    \
> +    ENABLE_IP_BUS1,                    \
> +};                            \

I don't understand why you would need a macro here. Isn't this constant
data that you can pass into multiple devices? The use of macros
definitely makes it worse than the original patch.

> +#define bus_div_clks(num)                        \
> +static struct samsung_div_clock bus##num_div_clks[] __initdata = {    \
> +    /* DIV_BUS */                            \
> +    DIV(CLK_DIV_PCLK_BUS##num_133, "div_pclk_bus"#num"_133",    \
> +            "aclk_bus"#num"_400", DIV_BUS##num, 0, 3),    \
> +};                                    \

To illustrate my point further: CLK_DIV_PCLK_BUS0/1/2 are all the
same, and so are DIV_BUS0/1/2, so you should not need to duplicate
the definitions at all but just call them 'CLK_DIV_PCLK_BUS'
and 'DIV_BUS'.

For the "aclk_bus"#num"_400" and "div_pclk_bus"#num"_133" strings,
I don't know what they refer to. Are you sure they have to be unique?

> +
> +#define bus_clk_regs(0)
> +#define bus_div_clks(0)
> +#define bus_gate_clks(0)
> +
> +#define bus_clk_regs(1)
> +#define bus_div_clks(1)
> +#define bus_gate_clks(1)
> +
> +static void __init exynos5433_cmu_bus_init(struct device_node *np)
> +{
> +    void __iomem *reg_base_bus0, *reg_base_bus1;
> +
> +    reg_base_bus0 = of_iomap(np, 0);
> +    reg_base_bus1 = of_iomap(np, 1);
> +
> +    bus0_ctx = samsung_clk_init(np, reg_base_bus0, BUS0_NR_CLKS);
> +    bus1_ctx = samsung_clk_init(np, reg_base_bus0, BUS0_NR_CLKS);
> +
> +    samsung_clk_register_div(bus0_ctx, bus0_div_clks,
> +                    ARRAY_SIZE(bus0_div_clks));
> +    samsung_clk_register_gate(bus0_ctx, bus0_gate_clks,
> +                    ARRAY_SIZE(bus0_gate_clks));
> +    samsung_clk_register_div(bus1_ctx, bus1_div_clks,
> +                    ARRAY_SIZE(bus1_div_clks));
> +    samsung_clk_register_gate(bus1_ctx, bus1_gate_clks,
> +                    ARRAY_SIZE(bus1_gate_clks));
> +
> +    samsung_clk_of_provider(np, bus0_ctx);
> +    samsung_clk_of_provider(np, bus1_ctx);
> +
> +}
> +CLK_OF_DECLARE(exynos5433_cmu_bus, "samsung,exynos5433-cmu-bus",
> +        exynos5433_cmu_bus_init);

This isn't helpful either: you really have two instances and should
not merge them together into one device node. This should look like

static void __init exynos5433_cmu_bus_init(struct device_node *np)
{
    void __iomem *reg_base_bus;

    reg_base_bus = of_iomap(np, 0);

    bus_ctx = samsung_clk_init(np, reg_base_bus, BUS_NR_CLKS);

    samsung_clk_register_div(bus_ctx, bus_div_clks,
                    ARRAY_SIZE(bus_div_clks));
    samsung_clk_register_gate(bus_ctx, bus_gate_clks,
                    ARRAY_SIZE(bus_gate_clks));

    samsung_clk_of_provider(np, bus0_ctx);
}

and get called three times.

	Arnd

  reply	other threads:[~2014-11-27 15:33 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-27  7:34 [PATCH 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC Chanwoo Choi
2014-11-27  7:34 ` [PATCH 01/19] pinctrl: exynos: Add support for Exynos5433 Chanwoo Choi
2014-11-27 10:26   ` [01/19] " Pankaj Dubey
2014-11-27 10:49     ` Chanwoo Choi
2014-11-27 11:45   ` [PATCH 01/19] " Arnd Bergmann
2014-11-27 12:14     ` Tomasz Figa
2014-11-27 12:36       ` Arnd Bergmann
2014-12-28 11:21   ` Tomasz Figa
2014-12-28 23:33     ` Chanwoo Choi
2014-11-27  7:34 ` [PATCH 02/19] clk: samsung: Add binding documentation for Exynos5433 clock controller Chanwoo Choi
2014-11-27 11:21   ` Mark Rutland
2014-11-27 11:29     ` Chanwoo Choi
2014-11-27  7:35 ` [PATCH 03/19] clk: samsung: exynos5433: Add clocks using common clock framework Chanwoo Choi
2014-11-27 11:48   ` [03/19] " Pankaj Dubey
2014-11-27 12:53     ` Chanwoo Choi
2014-11-28  1:57     ` Chanwoo Choi
2014-11-27  7:35 ` [PATCH 04/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 10/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain Chanwoo Choi
     [not found] ` <1417073716-22997-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-11-27  7:35   ` [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains Chanwoo Choi
2014-11-27 11:41     ` Arnd Bergmann
2014-11-27 11:56       ` Chanwoo Choi
     [not found]         ` <54771173.6090408-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-11-27 12:12           ` Sylwester Nawrocki
2014-11-27 12:14             ` Chanwoo Choi
2014-11-27 12:35             ` Arnd Bergmann
2014-11-27 12:58               ` Chanwoo Choi
2014-11-27 13:15                 ` Arnd Bergmann
     [not found]                   ` <CAGTfZH3KmwhJNFdmeWnujbbUbtLf5vSi6i2dbV62DeCtV7n4TQ@mail.gmail.com>
     [not found]                     ` <CAGTfZH3KmwhJNFdmeWnujbbUbtLf5vSi6i2dbV62DeCtV7n4TQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-11-27 14:02                       ` Arnd Bergmann
2014-11-27 15:17                         ` Chanwoo Choi
2014-11-27 15:33                           ` Arnd Bergmann [this message]
2014-11-27 15:44                             ` Chanwoo Choi
2014-11-27 15:51                               ` Arnd Bergmann
2014-11-27 15:58                                 ` Chanwoo Choi
2014-11-27  7:35 ` [PATCH 12/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 13/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 14/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain Chanwoo Choi
2014-11-27  7:35 ` [PATCH 15/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support Chanwoo Choi
2014-11-27 11:18   ` Catalin Marinas
     [not found]     ` <20141127111839.GD11511-M2fw3Uu6cmfZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2014-11-27 11:22       ` Chanwoo Choi
2014-11-27  7:35 ` [PATCH 16/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC Chanwoo Choi
2014-11-27 10:26   ` Marc Zyngier
2014-11-28 13:51     ` Chanwoo Choi
     [not found]   ` <1417073716-22997-17-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-11-27 11:18     ` Mark Rutland
2014-11-28 13:18       ` Chanwoo Choi
2014-11-28 14:00         ` Mark Rutland
2014-12-01  2:21           ` Chanwoo Choi
2014-12-02 10:42             ` Mark Rutland
2014-11-27  7:35 ` [PATCH 17/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433 Chanwoo Choi
2014-11-27  7:35 ` [PATCH 18/19] arm64: dts: exynos: Add SPI/PDMA " Chanwoo Choi
2014-11-27  7:35 ` [PATCH 19/19] serial: samsung: Add the support for Exynos5433 SoC Chanwoo Choi

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