[PATCH v4 0/3] Enable Inline crypto engine for kodiak and monaco

[PATCH v4 0/3] Enable Inline crypto engine for kodiak and monaco

[Neeraj Soni]

Document Inline Crypto Engine (ICE) handle for SDHC and add its device-tree
node to enable it for kodiak and monaco.

How this patch was tested:
- export ARCH=arm64
- export CROSS_COMPILE=aarch64-linux-gnu-
- make menuconfig
- make defconifg
- make DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/sdhci-msm.yaml dt_binding_check
- make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- CHECK_DTBS=y dtbs

---
Changes in v4:
- Added a new patch (3/3) for device tree changes for Monaco SoC.
- Updated commit subject of cover letter to reflect "monaco".
- Removed the text description of constraints from "description:" for "qcom,ice" and
  wrapped the code.
- Corrected the schema code to reflect the constraint of "qcom,ice" usage properly.

Changes in v3:
- Described the purpose for phandle in "description:" for "qcom,ice".
- Re-added the "if: required:" description for "qcom,ice" with proper
  encoding.
- Corrected the uppercase for base address and reg address space for ICE DT node.

Changes in v2:
- Removed the "if: required:" description for "qcom,ice" dt-binding
  as the ICE node is optional.
- Corrected the ICE dt node entry according to the dt-binding description.
- Added test details.

Changes in v1:
- Updated the dt-binding for ICE node.
- Added the dt node for ICE for kodiak.


Neeraj Soni (3):
  dt-bindings: mmc: sdhci-msm: Add ICE phandle
  arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC
  arm64: dts: qcom: monaco: enable the inline crypto engine for SDHC

 .../devicetree/bindings/mmc/sdhci-msm.yaml        | 15 +++++++++++++++
 arch/arm64/boot/dts/qcom/kodiak.dtsi              |  9 +++++++++
 arch/arm64/boot/dts/qcom/monaco.dtsi              |  9 +++++++++
 3 files changed, 33 insertions(+)

--
2.34.1

[PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Neeraj Soni]

Starting with sc7280(kodiak), the ICE will have its own device-tree node.
So add the qcom,ice property to reference it.

To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE
register region in the SDHCI node. Older SoCs without ICE remain valid as
no additional requirement is imposed.

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>

---

Some initial work is done by Abel here:
https://lore.kernel.org/all/ba3da82d-999b-b040-5230-36e60293e0fd@linaro.org/
and by Abhinaba here:
https://lore.kernel.org/all/20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-1-2a34d8d03c72@oss.qualcomm.com/

This patch adds the purpose and usage for phandle in the description and encodes
it properly in the schema.
---
 .../devicetree/bindings/mmc/sdhci-msm.yaml        | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 938be8228d66..9b902e0c8d09 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -140,6 +140,11 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: platform specific settings for DLL_CONFIG reg.
 
+  qcom,ice:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
+
   iommus:
     minItems: 1
     maxItems: 8
@@ -223,6 +228,16 @@ allOf:
             - const: cqhci
             - const: ice
 
+  - if:
+      required:
+        - qcom,ice
+    then:
+      properties:
+        reg-names:
+          not:
+            contains:
+              const: ice
+
 unevaluatedProperties: false
 
 examples:
-- 
2.34.1

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Krzysztof Kozlowski]

On Tue, Feb 17, 2026 at 10:55:24AM +0530, Neeraj Soni wrote:
> Starting with sc7280(kodiak), the ICE will have its own device-tree node.
> So add the qcom,ice property to reference it.
> 
> To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

> register region in the SDHCI node. Older SoCs without ICE remain valid as
> no additional requirement is imposed.
> 
> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
> 
> ---
> 
> Some initial work is done by Abel here:
> https://lore.kernel.org/all/ba3da82d-999b-b040-5230-36e60293e0fd@linaro.org/
> and by Abhinaba here:
> https://lore.kernel.org/all/20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-1-2a34d8d03c72@oss.qualcomm.com/
> 
> This patch adds the purpose and usage for phandle in the description and encodes
> it properly in the schema.
> ---
>  .../devicetree/bindings/mmc/sdhci-msm.yaml        | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> index 938be8228d66..9b902e0c8d09 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> @@ -140,6 +140,11 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description: platform specific settings for DLL_CONFIG reg.
>  
> +  qcom,ice:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      phandle to the Inline Crypto Engine (ICE) hardware block for this controller.


Srsly, I asked once and not much improved. What is explicitly written in
coding style which I asked you twice to read?

And how long is this line? Why such trivialities cannot be fixed and I
need to remind this every time?

> +
>    iommus:
>      minItems: 1
>      maxItems: 8
> @@ -223,6 +228,16 @@ allOf:
>              - const: cqhci
>              - const: ice
>  
> +  - if:
> +      required:
> +        - qcom,ice
> +    then:
> +      properties:
> +        reg-names:
> +          not:
> +            contains:
> +              const: ice

And reg is still 4? This is not correct syntax. You need to define
proper and final constraints per each device. I would write example, but
why... more things you could just ignore.

Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Neeraj Soni]

On 2/18/2026 1:46 AM, Krzysztof Kozlowski wrote:
> On Tue, Feb 17, 2026 at 10:55:24AM +0530, Neeraj Soni wrote:
>> Starting with sc7280(kodiak), the ICE will have its own device-tree node.
>> So add the qcom,ice property to reference it.
>>
>> To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE
> 
> Please wrap commit message according to Linux coding style / submission
> process (neither too early nor over the limit):
> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
> 
Ack. Will fix in next patch.

>> register region in the SDHCI node. Older SoCs without ICE remain valid as
>> no additional requirement is imposed.
>>
>> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>> Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
>> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
>> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
>>
>> ---
>>
>> Some initial work is done by Abel here:
>> https://lore.kernel.org/all/ba3da82d-999b-b040-5230-36e60293e0fd@linaro.org/
>> and by Abhinaba here:
>> https://lore.kernel.org/all/20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-1-2a34d8d03c72@oss.qualcomm.com/
>>
>> This patch adds the purpose and usage for phandle in the description and encodes
>> it properly in the schema.
>> ---
>>  .../devicetree/bindings/mmc/sdhci-msm.yaml        | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
>> index 938be8228d66..9b902e0c8d09 100644
>> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
>> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
>> @@ -140,6 +140,11 @@ properties:
>>      $ref: /schemas/types.yaml#/definitions/uint32
>>      description: platform specific settings for DLL_CONFIG reg.
>>  
>> +  qcom,ice:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
> 
> 
> Srsly, I asked once and not much improved. What is explicitly written in
> coding style which I asked you twice to read?
>
I have attempted to modifiy it as per the comment you gave in v3 here:
https://lore.kernel.org/all/b6e510da-b369-4c43-b9a1-455478af4948@kernel.org/

I will rephrase it to explain the usage better in next patch.

> And how long is this line? Why such trivialities cannot be fixed and I
> need to remind this every time?
> 
It is 83 character long but i understand now you expect it to be wrapped 
at 75 as per kernel coding style. I missed it and stuck to the limit
dt_binding_check tool allowed. Will fix in next patch.

>> +
>>    iommus:
>>      minItems: 1
>>      maxItems: 8
>> @@ -223,6 +228,16 @@ allOf:
>>              - const: cqhci
>>              - const: ice
>>  
>> +  - if:
>> +      required:
>> +        - qcom,ice
>> +    then:
>> +      properties:
>> +        reg-names:
>> +          not:
>> +            contains:
>> +              const: ice
> 
> And reg is still 4? This is not correct syntax. You need to define
> proper and final constraints per each device. I would write example, but
> why... more things you could just ignore.
>
I had included changes for reg in v3:
https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/

but those were not reviewed so i assume them to be incorrect and dropped it.
Will fix this in next patch and post.

 
> Best regards,
> Krzysztof
> 
Regards,
Neeraj

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Krzysztof Kozlowski]

On 19/02/2026 06:38, Neeraj Soni wrote:
>>> +  qcom,ice:
>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>> +    description:
>>> +      phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
>>
>>
>> Srsly, I asked once and not much improved. What is explicitly written in
>> coding style which I asked you twice to read?
>>
> I have attempted to modifiy it as per the comment you gave in v3 here:
> https://lore.kernel.org/all/b6e510da-b369-4c43-b9a1-455478af4948@kernel.org/
> 
> I will rephrase it to explain the usage better in next patch.
> 
>> And how long is this line? Why such trivialities cannot be fixed and I
>> need to remind this every time?
>>
> It is 83 character long but i understand now you expect it to be wrapped 
> at 75 as per kernel coding style. I missed it and stuck to the limit

75?



Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Neeraj Soni]

On 2/19/2026 12:50 PM, Krzysztof Kozlowski wrote:
> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>> +  qcom,ice:
>>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>>> +    description:
>>>> +      phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
>>>
>>>
>>> Srsly, I asked once and not much improved. What is explicitly written in
>>> coding style which I asked you twice to read?
>>>
>> I have attempted to modifiy it as per the comment you gave in v3 here:
>> https://lore.kernel.org/all/b6e510da-b369-4c43-b9a1-455478af4948@kernel.org/
>>
>> I will rephrase it to explain the usage better in next patch.
>>
>>> And how long is this line? Why such trivialities cannot be fixed and I
>>> need to remind this every time?
>>>
>> It is 83 character long but i understand now you expect it to be wrapped 
>> at 75 as per kernel coding style. I missed it and stuck to the limit
> 
> 75?
> 
Apologies for typo. Wanted to right 80:
https://www.kernel.org/doc/html/v4.10/process/coding-style.html

> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Krzysztof Kozlowski]

On 19/02/2026 06:38, Neeraj Soni wrote:
>>>  
>>> +  - if:
>>> +      required:
>>> +        - qcom,ice
>>> +    then:
>>> +      properties:
>>> +        reg-names:
>>> +          not:
>>> +            contains:
>>> +              const: ice
>>
>> And reg is still 4? This is not correct syntax. You need to define
>> proper and final constraints per each device. I would write example, but
>> why... more things you could just ignore.
>>
> I had included changes for reg in v3:
> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
> 
> but those were not reviewed so i assume them to be incorrect and dropped it.
> Will fix this in next patch and post.
> 
Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
2 entries, not 1-3 as previous patch said.

You need to embed the ifs:

189   - if:
190       properties:
191         compatible:
192           contains:
193             enum:
194               - qcom,sdhci-msm-v4
195     then:

here you add one more if:

196       properties:
197         reg:


198           minItems: 2
199           items:
200             - description: Host controller register map
201             - description: SD Core register map
202             - description: CQE register map
203             - description: Inline Crypto Engine register map
204         reg-names:
205           minItems: 2
206           items:
207             - const: hc
208             - const: core
209             - const: cqhci
210             - const: ice
211     else:

and here as well.

212       properties:
213         reg:
214           minItems: 1
215           items:
216             - description: Host controller register map
217             - description: CQE register map
218             - description: Inline Crypto Engine register map
219         reg-names:
220           minItems: 1
221           items:
222             - const: hc
223             - const: cqhci
224             - const: ice

At least that's the simplest solution I see now.

Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Neeraj Soni]

On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>  
>>>> +  - if:
>>>> +      required:
>>>> +        - qcom,ice
>>>> +    then:
>>>> +      properties:
>>>> +        reg-names:
>>>> +          not:
>>>> +            contains:
>>>> +              const: ice
>>>
>>> And reg is still 4? This is not correct syntax. You need to define
>>> proper and final constraints per each device. I would write example, but
>>> why... more things you could just ignore.
>>>
>> I had included changes for reg in v3:
>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>
>> but those were not reviewed so i assume them to be incorrect and dropped it.
>> Will fix this in next patch and post.
>>
> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
> 2 entries, not 1-3 as previous patch said.
> 
This is not clear to me. Here:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
it says the entries should be 1-4 and there are no v5 specific constraints.
So i made it 1-3 while adding qcom-ice constraint.

> You need to embed the ifs:
> 
> 189   - if:
> 190       properties:
> 191         compatible:
> 192           contains:
> 193             enum:
> 194               - qcom,sdhci-msm-v4
> 195     then:
> 
> here you add one more if:
> 
Acked. Will add in next patch.

> 196       properties:
> 197         reg:
> 
> 
> 198           minItems: 2
> 199           items:
> 200             - description: Host controller register map
> 201             - description: SD Core register map
> 202             - description: CQE register map
> 203             - description: Inline Crypto Engine register map
> 204         reg-names:
> 205           minItems: 2
> 206           items:
> 207             - const: hc
> 208             - const: core
> 209             - const: cqhci
> 210             - const: ice
> 211     else:
> 
> and here as well.
> 
Acked. Will add in next patch.

> 212       properties:
> 213         reg:
> 214           minItems: 1
> 215           items:
> 216             - description: Host controller register map
> 217             - description: CQE register map
> 218             - description: Inline Crypto Engine register map
> 219         reg-names:
> 220           minItems: 1
> 221           items:
> 222             - const: hc
> 223             - const: cqhci
> 224             - const: ice
> 
> At least that's the simplest solution I see now.
> 
> Best regards,
> Krzysztof
> 
Regards,
Neeraj

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Krzysztof Kozlowski]

On 02/03/2026 08:45, Neeraj Soni wrote:
> 
> 
> On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
>> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>>  
>>>>> +  - if:
>>>>> +      required:
>>>>> +        - qcom,ice
>>>>> +    then:
>>>>> +      properties:
>>>>> +        reg-names:
>>>>> +          not:
>>>>> +            contains:
>>>>> +              const: ice
>>>>
>>>> And reg is still 4? This is not correct syntax. You need to define
>>>> proper and final constraints per each device. I would write example, but
>>>> why... more things you could just ignore.
>>>>
>>> I had included changes for reg in v3:
>>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>>
>>> but those were not reviewed so i assume them to be incorrect and dropped it.
>>> Will fix this in next patch and post.
>>>
>> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
>> 2 entries, not 1-3 as previous patch said.
>>
> This is not clear to me. Here:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
> it says the entries should be 1-4 and there are no v5 specific constraints.

There are, just scroll.

> So i made it 1-3 while adding qcom-ice constraint.
> 


Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Krzysztof Kozlowski]

On 02/03/2026 08:48, Krzysztof Kozlowski wrote:
> On 02/03/2026 08:45, Neeraj Soni wrote:
>>
>>
>> On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
>>> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>>>  
>>>>>> +  - if:
>>>>>> +      required:
>>>>>> +        - qcom,ice
>>>>>> +    then:
>>>>>> +      properties:
>>>>>> +        reg-names:
>>>>>> +          not:
>>>>>> +            contains:
>>>>>> +              const: ice
>>>>>
>>>>> And reg is still 4? This is not correct syntax. You need to define
>>>>> proper and final constraints per each device. I would write example, but
>>>>> why... more things you could just ignore.
>>>>>
>>>> I had included changes for reg in v3:
>>>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>>>
>>>> but those were not reviewed so i assume them to be incorrect and dropped it.
>>>> Will fix this in next patch and post.
>>>>
>>> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
>>> 2 entries, not 1-3 as previous patch said.
>>>
>> This is not clear to me. Here:
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
>> it says the entries should be 1-4 and there are no v5 specific constraints.
> 
> There are, just scroll.

Here:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n212

> 
>> So i made it 1-3 while adding qcom-ice constraint.
>>
> 
> 
> Best regards,
> Krzysztof


Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Neeraj Soni]

On 3/2/2026 2:27 PM, Krzysztof Kozlowski wrote:
> On 02/03/2026 08:48, Krzysztof Kozlowski wrote:
>> On 02/03/2026 08:45, Neeraj Soni wrote:
>>>
>>>
>>> On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
>>>> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>>>>  
>>>>>>> +  - if:
>>>>>>> +      required:
>>>>>>> +        - qcom,ice
>>>>>>> +    then:
>>>>>>> +      properties:
>>>>>>> +        reg-names:
>>>>>>> +          not:
>>>>>>> +            contains:
>>>>>>> +              const: ice
>>>>>>
>>>>>> And reg is still 4? This is not correct syntax. You need to define
>>>>>> proper and final constraints per each device. I would write example, but
>>>>>> why... more things you could just ignore.
>>>>>>
>>>>> I had included changes for reg in v3:
>>>>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>>>>
>>>>> but those were not reviewed so i assume them to be incorrect and dropped it.
>>>>> Will fix this in next patch and post.
>>>>>
>>>> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
>>>> 2 entries, not 1-3 as previous patch said.
>>>>
>>> This is not clear to me. Here:
>>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
>>> it says the entries should be 1-4 and there are no v5 specific constraints.
>>
>> There are, just scroll.
> 
> Here:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n212
> 
Yes i had looked at this but, as i understand, this constraints the minItems: not the
maxItems: and in your comment here:

https://lore.kernel.org/all/21a87714-cd11-4217-a2aa-82fddc3a8530@kernel.org/

you expect v5 entries to be constrained to 1-2 and not 1-3. So, as i understand from here:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n78

the v5 can have 1-4 entries without "qcom,ice" and 1-3 with it which is what i had posted.
 
>>
>>> So i made it 1-3 while adding qcom-ice constraint.
>>>
>>
>>
>> Best regards,
>> Krzysztof
> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Krzysztof Kozlowski]

On 02/03/2026 12:25, Neeraj Soni wrote:
> 
> 
> On 3/2/2026 2:27 PM, Krzysztof Kozlowski wrote:
>> On 02/03/2026 08:48, Krzysztof Kozlowski wrote:
>>> On 02/03/2026 08:45, Neeraj Soni wrote:
>>>>
>>>>
>>>> On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
>>>>> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>>>>>  
>>>>>>>> +  - if:
>>>>>>>> +      required:
>>>>>>>> +        - qcom,ice
>>>>>>>> +    then:
>>>>>>>> +      properties:
>>>>>>>> +        reg-names:
>>>>>>>> +          not:
>>>>>>>> +            contains:
>>>>>>>> +              const: ice
>>>>>>>
>>>>>>> And reg is still 4? This is not correct syntax. You need to define
>>>>>>> proper and final constraints per each device. I would write example, but
>>>>>>> why... more things you could just ignore.
>>>>>>>
>>>>>> I had included changes for reg in v3:
>>>>>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>>>>>
>>>>>> but those were not reviewed so i assume them to be incorrect and dropped it.
>>>>>> Will fix this in next patch and post.
>>>>>>
>>>>> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
>>>>> 2 entries, not 1-3 as previous patch said.
>>>>>
>>>> This is not clear to me. Here:
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
>>>> it says the entries should be 1-4 and there are no v5 specific constraints.
>>>
>>> There are, just scroll.
>>
>> Here:
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n212
>>
> Yes i had looked at this but, as i understand, this constraints the minItems: not the
> maxItems: and in your comment here:
> 
> https://lore.kernel.org/all/21a87714-cd11-4217-a2aa-82fddc3a8530@kernel.org/
> 
> you expect v5 entries to be constrained to 1-2 and not 1-3. So, as i understand from here:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n78
> 
> the v5 can have 1-4 entries without "qcom,ice" and 1-3 with it which is what i had posted.

We have long discussion and you are just not replying to the problem. I
am done here. I wrote already what is wrong and what I expect.

Repeating the same as before in the FIRST comment: Your patch allows
incorrectly four reg entries for v4 and there reg entries for v5.

That's a NAK.

Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

[Neeraj Soni]

On 3/2/2026 10:08 PM, Krzysztof Kozlowski wrote:
> On 02/03/2026 12:25, Neeraj Soni wrote:
>>
>>
>> On 3/2/2026 2:27 PM, Krzysztof Kozlowski wrote:
>>> On 02/03/2026 08:48, Krzysztof Kozlowski wrote:
>>>> On 02/03/2026 08:45, Neeraj Soni wrote:
>>>>>
>>>>>
>>>>> On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
>>>>>> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>>>>>>  
>>>>>>>>> +  - if:
>>>>>>>>> +      required:
>>>>>>>>> +        - qcom,ice
>>>>>>>>> +    then:
>>>>>>>>> +      properties:
>>>>>>>>> +        reg-names:
>>>>>>>>> +          not:
>>>>>>>>> +            contains:
>>>>>>>>> +              const: ice
>>>>>>>>
>>>>>>>> And reg is still 4? This is not correct syntax. You need to define
>>>>>>>> proper and final constraints per each device. I would write example, but
>>>>>>>> why... more things you could just ignore.
>>>>>>>>
>>>>>>> I had included changes for reg in v3:
>>>>>>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>>>>>>
>>>>>>> but those were not reviewed so i assume them to be incorrect and dropped it.
>>>>>>> Will fix this in next patch and post.
>>>>>>>
>>>>>> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
>>>>>> 2 entries, not 1-3 as previous patch said.
>>>>>>
>>>>> This is not clear to me. Here:
>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
>>>>> it says the entries should be 1-4 and there are no v5 specific constraints.
>>>>
>>>> There are, just scroll.
>>>
>>> Here:
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n212
>>>
>> Yes i had looked at this but, as i understand, this constraints the minItems: not the
>> maxItems: and in your comment here:
>>
>> https://lore.kernel.org/all/21a87714-cd11-4217-a2aa-82fddc3a8530@kernel.org/
>>
>> you expect v5 entries to be constrained to 1-2 and not 1-3. So, as i understand from here:
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n78
>>
>> the v5 can have 1-4 entries without "qcom,ice" and 1-3 with it which is what i had posted.
> 
> We have long discussion and you are just not replying to the problem. I
> am done here. I wrote already what is wrong and what I expect.
> 
> Repeating the same as before in the FIRST comment: Your patch allows
> incorrectly four reg entries for v4 and there reg entries for v5.
> 
Sure. I will test and post the new patch with constraints for v4 and v5.

> That's a NAK.
> 
> Best regards,
> Krzysztof
> 
Regards,
Neeraj

[PATCH v4 2/3] arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC

[Neeraj Soni]

Add an ICE node to kodiak SoC description and enable it by adding a
phandle to the SDHC node.

Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index c2ccbb67f800..de01a6669522 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1045,6 +1045,8 @@ sdhc_1: mmc@7c4000 {
 			qcom,dll-config = <0x0007642c>;
 			qcom,ddr-config = <0x80040868>;
 
+			qcom,ice = <&sdhc_ice>;
+
 			mmc-ddr-1_8v;
 			mmc-hs200-1_8v;
 			mmc-hs400-1_8v;
@@ -1071,6 +1073,13 @@ opp-384000000 {
 			};
 		};
 
+		sdhc_ice: crypto@7c8000 {
+			compatible = "qcom,sc7280-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x007c8000 0x0 0x18000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+		};
+
 		gpi_dma0: dma-controller@900000 {
 			#dma-cells = <3>;
 			compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
-- 
2.34.1

[PATCH v4 3/3] arm64: dts: qcom: monaco: enable the inline crypto engine for SDHC

[Neeraj Soni]

Add an ICE node to monaco SoC description and enable it by adding a
phandle to the SDHC node.
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 816fa2af8a9a..365af78b01ae 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4202,6 +4202,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			supports-cqe;
 			dma-coherent;
 
+			qcom,ice = <&sdhc_ice>;
+
 			status = "disabled";
 
 			sdhc1_opp_table: opp-table {
@@ -4229,6 +4231,13 @@ opp-384000000 {
 			};
 		};
 
+		sdhc_ice: crypto@87c8000 {
+			compatible = "qcom,qcs8300-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x087c8000 0x0 0x18000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+		};
+
 		usb_1_hsphy: phy@8904000 {
 			compatible = "qcom,qcs8300-usb-hs-phy",
 				     "qcom,usb-snps-hs-7nm-phy";
-- 
2.34.1