From: rajpat@codeaurora.org
To: Stephen Boyd <swboyd@chromium.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, rnayak@codeaurora.org,
saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com,
skakit@codeaurora.org, mka@chromium.org, dianders@chromium.org,
Roja Rani Yarubandi <rojay@codeaurora.org>
Subject: Re: [PATCH V9 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
Date: Wed, 22 Sep 2021 18:01:13 +0530 [thread overview]
Message-ID: <21d14dd0bfa945ee617ed4b86b4495ee@codeaurora.org> (raw)
On 2021-09-21 23:47, Stephen Boyd wrote:
> Quoting Rajesh Patil (2021-09-21 03:39:02)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 2fbcb0a..b65c5da 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -536,24 +555,425 @@
>> qupv3_id_0: geniqup@9c0000 {
>> compatible = "qcom,geni-se-qup";
>> reg = <0 0x009c0000 0 0x2000>;
>> - clock-names = "m-ahb", "s-ahb";
>> clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>> <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
>> + clock-names = "m-ahb", "s-ahb";
>> #address-cells = <2>;
>> #size-cells = <2>;
>> ranges;
>> + iommus = <&apps_smmu 0x123 0x0>;
>> status = "disabled";
>>
>> + i2c0: i2c@980000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00980000 0 0x4000>;
>> + clocks = <&gcc
>> GCC_QUPV3_WRAP0_S0_CLK>;
>> + clock-names = "se";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c0_data_clk>;
>> + interrupts = <GIC_SPI 601
>> IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt
>> MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc
>> MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc
>> MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core",
>> "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi0: spi@980000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00980000 0 0x4000>;
>> + clocks = <&gcc
>> GCC_QUPV3_WRAP0_S0_CLK>;
>> + clock-names = "se";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi0_data_clk>,
>> <&qup_spi0_cs>, <&qup_spi0_cs_gpio>;
>
> This should only have qup_spi0_data_clk and qup_spi0_cs, not
> qup_spi0_cs_gpio. Both qup controlled and gpio controlled options are
> provided in case a board wants to use the qup version of chipselect,
> but
> having them both used by default leads to conflicts and confusion. This
> same comment applies to all spi pinctrl properties in this file. Please
> keep the cs_gpio variants though so that boards can use them if they
> want. They will be unused, but that's OK.
Okay. Shall we remove only "<&qup_spiN_cs_gpio>" in each SPI node?
>
>> + interrupts = <GIC_SPI 601
>> IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 =
>> <&qup_opp_table>;
>> + interconnects = <&clk_virt
>> MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc
>> MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core",
>> "qup-config";
>> + status = "disabled";
>> + };
>> +
next reply other threads:[~2021-09-22 12:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-22 12:31 rajpat [this message]
2021-09-22 14:54 ` [PATCH V9 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Doug Anderson
2021-09-23 10:13 ` rajpat
-- strict thread matches above, loose matches on Subject: below --
2021-09-21 10:38 [PATCH V9 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-09-21 10:39 ` [PATCH V9 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-09-21 18:17 ` Stephen Boyd
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