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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 1bpIUoP_3vW_qoj10l0vfPDgUNk0hcnt X-Authority-Analysis: v=2.4 cv=R5kz39RX c=1 sm=1 tr=0 ts=6a031a9a cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=o6O9cqeRkQFRtQiNs1sA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDEyNyBTYWx0ZWRfXwwzF/y4Fpf1f KZKxP7qO07C/qxaq/srnBjA8lc9lYpiUzOem5+K533MJ3faF4W/NybzwCjQ+SiONSTmd3+XZKbZ AaVsEfHGCyxtAXtTZ6rUzVWBfe3ZQwtdQYcqiC2nNNgfUWMVRMLa3mn3ADJtSCoMB3XYCKnQtbb CkOnRoQMLnmRobpeYw2NzNvwpUqrLA5Yk6tqNieQYMuP5OpGo1MCLFAtljVtUTfpCUQDjxGH6u0 ksvbvXruRPoTbLeAsiB9VGpGsFBH827YcqPzXzfH4c7i1dpr8kGuqH/0N0TzO0SCjKrsZFFsGCm YmCeVs8xz+xAPhQWEKFeqMqSBlmr2KYafa3g+vp6mO7YBhBedGtVy3MY6/NRVF9poEMLQlzmLzf M/E4CCx+jUVHE7U1YtpT4nBuneGzXBxfujguq/rJtIMh8719cygZg4W2+MEcd+AfXF7UVKlOj5J Bb0JEqSfS+j5ZSv037Q== X-Proofpoint-GUID: 1bpIUoP_3vW_qoj10l0vfPDgUNk0hcnt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120127 On 5/9/2026 1:02 AM, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [High] Inconsistent eGPIO (Embedded GPIO) hardware configuration. > -- > > commit a63bd64b64bae3d595ab0e510830b193aeee7ba6 > Author: Komal Bajaj > > pinctrl: qcom: Add Shikra pinctrl driver > > Add pinctrl driver for TLMM block found in Shikra SoC. > >> diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c >> new file mode 100644 >> index 0000000000000..f063e73e5bbd5 >> --- /dev/null >> +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c > [ ... ] > >> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ >> + { \ >> + .grp = PINCTRL_PINGROUP("gpio" #id, \ >> + gpio##id##_pins, \ >> + ARRAY_SIZE(gpio##id##_pins)), \ >> + .funcs = (int[]){ \ >> + msm_mux_gpio, /* gpio mode */ \ >> + msm_mux_##f1, \ >> + msm_mux_##f2, \ >> + msm_mux_##f3, \ >> + msm_mux_##f4, \ >> + msm_mux_##f5, \ >> + msm_mux_##f6, \ >> + msm_mux_##f7, \ >> + msm_mux_##f8, \ >> + msm_mux_##f9, \ >> + msm_mux_##f10, \ >> + msm_mux_##f11 /* egpio mode */ \ >> + }, \ >> + .nfuncs = 12, \ >> + .ctl_reg = REG_SIZE * id, \ >> + .io_reg = 0x4 + REG_SIZE * id, \ >> + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ >> + .intr_status_reg = 0xc + REG_SIZE * id, \ >> + .mux_bit = 2, \ >> + .pull_bit = 0, \ >> + .drv_bit = 6, \ >> + .egpio_enable = 12, \ >> + .egpio_present = 11, \ > [ ... ] > >> +static const struct msm_pingroup shikra_groups[] = { >> + [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _), >> + [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _), > [ ... ] > >> +static const struct msm_pinctrl_soc_data shikra_tlmm = { >> + .pins = shikra_pins, >> + .npins = ARRAY_SIZE(shikra_pins), >> + .functions = shikra_functions, >> + .nfunctions = ARRAY_SIZE(shikra_functions), >> + .groups = shikra_groups, >> + .ngroups = ARRAY_SIZE(shikra_groups), >> + .ngpios = 166, >> + .wakeirq_map = shikra_mpm_map, >> + .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), >> + .egpio_func = 11, >> +}; > Is the hardware eGPIO configuration completely implemented? > > The driver configures .egpio_func = 11 in shikra_tlmm and defines > egpio_enable = 12 and egpio_present = 11 bits in the PINGROUP macro, indicating > that eGPIO is mapped to function index 11. > > However, the driver does not define the msm_mux_egpio enum, the egpio_groups > array, or MSM_PIN_FUNCTION(egpio). Instead, it passes the dummy function _ for > the 11th mux slot (f11) across all pins in shikra_groups. > > Because .egpio_func is non-zero, the core pinctrl-msm driver will actively > clear bit 12 (egpio_enable) of ctl_reg during any pin mux operation if bit 11 > is set. > > If the SoC does not support eGPIO and these bits serve another purpose, could > this unexpectedly change the hardware state on every pin mux change? Conversely, > if it does support eGPIO, it appears the feature would be unusable because it > cannot be selected via the device tree since the function is not exposed. > > Could you clarify if eGPIO is intended to be supported on this SoC? Yes, Shikra doesn’t seem to support eGPIO. I’ll remove the eGPIO-related bits and .egpio_func to avoid any unintended behavior. Thanks Komal