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Am Mittwoch, 16. Oktober 2024, 01:20:51 CEST schrieb Marek Vasut: > The IOMUXC controller description is almost identical on i.MX35/5x/6 SoCs, > except for the configuration bits which differ across SoCs. Rename the > fsl,imx6ul-pinctrl.yaml to fsl,imx35-pinctrl.yaml, fill in compatible > strings for the other SoCs and fill in the various bits into desciption. > This way, i.MX35/5x/6 series SoCs can all be converted to YAML DT. Remove > the old text DT bindings description. >=20 > Signed-off-by: Marek Vasut > --- > Cc: Conor Dooley > Cc: Dong Aisheng > Cc: Fabio Estevam > Cc: Jacky Bai > Cc: Krzysztof Kozlowski > Cc: Linus Walleij > Cc: Pengutronix Kernel Team > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Shawn Guo > Cc: devicetree@vger.kernel.org > Cc: imx@lists.linux.dev > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-gpio@vger.kernel.org > --- > .../bindings/pinctrl/fsl,imx35-pinctrl.txt | 33 -------- > ...ul-pinctrl.yaml =3D> fsl,imx35-pinctrl.yaml} | 79 +++++++++++++++++-- > .../bindings/pinctrl/fsl,imx50-pinctrl.txt | 32 -------- > .../bindings/pinctrl/fsl,imx51-pinctrl.txt | 32 -------- > .../bindings/pinctrl/fsl,imx53-pinctrl.txt | 32 -------- > .../bindings/pinctrl/fsl,imx6dl-pinctrl.txt | 38 --------- > .../bindings/pinctrl/fsl,imx6q-pinctrl.txt | 38 --------- > .../bindings/pinctrl/fsl,imx6sl-pinctrl.txt | 39 --------- > .../bindings/pinctrl/fsl,imx6sll-pinctrl.txt | 40 ---------- > .../bindings/pinctrl/fsl,imx6sx-pinctrl.txt | 36 --------- > 10 files changed, 72 insertions(+), 327 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx35-p= inctrl.txt > rename Documentation/devicetree/bindings/pinctrl/{fsl,imx6ul-pinctrl.yam= l =3D> fsl,imx35-pinctrl.yaml} (51%) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx50-p= inctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx51-p= inctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx53-p= inctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-= pinctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6q-p= inctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-= pinctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sll= =2Dpinctrl.txt > delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-= pinctrl.txt >=20 > [snip] > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl= =2Eyaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml > similarity index 51% > rename from Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.= yaml > rename to Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml > index 906b264a9e3cd..780d5fe0137e5 100644 > --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml > @@ -1,10 +1,10 @@ > # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > %YAML 1.2 > --- > -$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# > +$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > =20 > -title: Freescale IMX6UL IOMUX Controller > +title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller > =20 > maintainers: > - Dong Aisheng > @@ -19,6 +19,15 @@ allOf: > properties: > compatible: > enum: > + - fsl,imx35-iomuxc > + - fsl,imx50-iomuxc > + - fsl,imx51-iomuxc > + - fsl,imx53-iomuxc imx50.dtsi is using > "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; So either the .dtsi or this schema needs to be adjusted. > + - fsl,imx6dl-iomuxc > + - fsl,imx6q-iomuxc > + - fsl,imx6sl-iomuxc > + - fsl,imx6sll-iomuxc > + - fsl,imx6sx-iomuxc > - fsl,imx6ul-iomuxc > - fsl,imx6ull-iomuxc-snvs > =20 > @@ -39,9 +48,9 @@ patternProperties: > each entry consists of 6 integers and represents the mux and c= onfig > setting for one pin. The first 5 integers mux_val input_val> are specified using a PIN_FUNC_ID macro, wh= ich can > - be found in . The last int= eger > + be found in . The la= st integer > CONFIG is the pad setting value like pull-up on this pin. Plea= se > - refer to i.MX6UL Reference Manual for detailed CONFIG settings. > + refer to matching i.MX Reference Manual for detailed CONFIG se= ttings. > $ref: /schemas/types.yaml#/definitions/uint32-matrix > items: > items: > @@ -56,7 +65,41 @@ patternProperties: > - description: | > "input_val" indicates the select input value to be appli= ed. > - description: | > - "pad_setting" indicates the pad configuration value to b= e applied: > + "pad_setting" indicates the pad configuration value to b= e applied. > + Common i.MX35 > + PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) > + PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) > + PAD_CTL_HYS (1 << 8) > + PAD_CTL_PKE (1 << 7) > + PAD_CTL_PUE (1 << 6) > + PAD_CTL_PUS_100K_DOWN (0 << 4) > + PAD_CTL_PUS_47K_UP (1 << 4) > + PAD_CTL_PUS_100K_UP (2 << 4) > + PAD_CTL_PUS_22K_UP (3 << 4) > + PAD_CTL_ODE_CMOS (0 << 3) > + PAD_CTL_ODE_OPENDRAIN (1 << 3) > + PAD_CTL_DSE_NOMINAL (0 << 1) > + PAD_CTL_DSE_HIGH (1 << 1) > + PAD_CTL_DSE_MAX (2 << 1) > + PAD_CTL_SRE_FAST (1 << 0) > + PAD_CTL_SRE_SLOW (0 << 0) > + Common i.MX50/i.MX51/i.MX53 bits > + PAD_CTL_HVE (1 << 13) > + PAD_CTL_HYS (1 << 8) > + PAD_CTL_PKE (1 << 7) > + PAD_CTL_PUE (1 << 6) > + PAD_CTL_PUS_100K_DOWN (0 << 4) > + PAD_CTL_PUS_47K_UP (1 << 4) > + PAD_CTL_PUS_100K_UP (2 << 4) > + PAD_CTL_PUS_22K_UP (3 << 4) > + PAD_CTL_ODE (1 << 3) > + PAD_CTL_DSE_LOW (0 << 1) > + PAD_CTL_DSE_MED (1 << 1) > + PAD_CTL_DSE_HIGH (2 << 1) > + PAD_CTL_DSE_MAX (3 << 1) > + PAD_CTL_SRE_FAST (1 << 0) > + PAD_CTL_SRE_SLOW (0 << 0) > + Common i.MX6 bits > PAD_CTL_HYS (1 << 16) > PAD_CTL_PUS_100K_DOWN (0 << 14) > PAD_CTL_PUS_47K_UP (1 << 14) > @@ -69,6 +112,11 @@ patternProperties: > PAD_CTL_SPEED_MED (1 << 6) > PAD_CTL_SPEED_HIGH (3 << 6) > PAD_CTL_DSE_DISABLE (0 << 3) > + PAD_CTL_SRE_FAST (1 << 0) > + PAD_CTL_SRE_SLOW (0 << 0) > + i.MX6SL/MX6SLL specific bits > + PAD_CTL_LVE (1 << 22) (MX6SL/SLL o= nly) Is this comment 'MX6SL/SLL only' really needed? This bit is already in the i.MX6SL/MX6SLL only section. Despite that, this looks good. Best regards, Alexander > + i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits > PAD_CTL_DSE_260ohm (1 << 3) > PAD_CTL_DSE_130ohm (2 << 3) > PAD_CTL_DSE_87ohm (3 << 3) > @@ -76,8 +124,14 @@ patternProperties: > PAD_CTL_DSE_52ohm (5 << 3) > PAD_CTL_DSE_43ohm (6 << 3) > PAD_CTL_DSE_37ohm (7 << 3) > - PAD_CTL_SRE_FAST (1 << 0) > - PAD_CTL_SRE_SLOW (0 << 0) > + i.MX6DL/i.MX6Q/i.MX6SL specific bits > + PAD_CTL_DSE_240ohm (1 << 3) > + PAD_CTL_DSE_120ohm (2 << 3) > + PAD_CTL_DSE_80ohm (3 << 3) > + PAD_CTL_DSE_60ohm (4 << 3) > + PAD_CTL_DSE_48ohm (5 << 3) > + PAD_CTL_DSE_40ohm (6 << 3) > + PAD_CTL_DSE_34ohm (7 << 3) > =20 > required: > - fsl,pins > [snip] =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/