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On 2025/8/27 01:51, Conor Dooley wrote: > Subject: > Re: [PATCH v3 1/3] spi: dt-bindings: add Amlogic A113L2 SFC > From: > Conor Dooley > Date: > 2025/8/27 01:51 > > To: > xianwei.zhao@amlogic.com > CC: > Mark Brown , Rob Herring , > Krzysztof Kozlowski , Conor Dooley > , Liang Yang , Feng Chen > , linux-spi@vger.kernel.org, > devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, > linux-amlogic@lists.infradead.org > > > On Tue, Aug 26, 2025 at 10:10:09AM +0800, Xianwei Zhao via B4 Relay wrote: >> From: Feng Chen >> >> The Flash Controller is derived by adding an SPI path to the original >> raw NAND controller. This controller supports two modes: raw mode and >> SPI mode. The raw mode has already been implemented in the community, >> and the SPI mode is described here. >> >> Add bindings for Amlogic A113L2 SPI Flash Controller. >> >> Signed-off-by: Feng Chen >> Signed-off-by: Xianwei Zhao >> --- >> .../devicetree/bindings/spi/amlogic,a4-spifc.yaml | 82 ++++++++++++++++++++++ >> 1 file changed, 82 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml >> new file mode 100644 >> index 000000000000..80a89408a832 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml >> @@ -0,0 +1,82 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved >> +%YAML 1.2 >> +--- >> +$id:http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml# >> +$schema:http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: SPI flash controller for Amlogic ARM SoCs >> + >> +maintainers: >> + - Liang Yang >> + - Feng Chen >> + - Xianwei Zhao >> + >> +description: >> + The Amlogic SPI flash controller is an extended version of the Amlogic NAND >> + flash controller. It supports SPI Nor Flash and SPI NAND Flash(where the Host >> + ECC HW engine could be enabled). >> + >> +allOf: >> + - $ref: /schemas/spi/spi-controller.yaml# >> + >> +properties: >> + compatible: >> + const: amlogic,a4-spifc >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: clock apb gate >> + - description: clock used for the controller >> + >> + clock-names: >> + items: >> + - const: gate >> + - const: core >> + >> + interrupts: >> + maxItems: 1 >> + >> + amlogic,rx-adj: >> + description: >> + Adjust sample timing for RX, Sampling time move later by 1 bus clock. > By 1 bus clock? Or by up to 3? I'd suggest rewording this to something > like "Number of clock cycles by which sampling is delayed" or along > those lines. > Will do. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [0, 1, 2, 3] >> + default: 0 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + sfc0: spi@fe08d000 { >> + compatible = "amlogic,a4-spifc"; >> + reg = <0xfe08d000 0x800>; >> + clocks = <&clkc_periphs 31>, >> + <&clkc_periphs 102>; >> + clock-names = "gate", "core"; >> + >> + pinctrl-0 = <&spiflash_default>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + flash@0 { >> + compatible = "spi-nand"; >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + nand-ecc-engine = <&sfc0>; >> + nand-ecc-strength = <8>; >> + nand-ecc-step-size = <512>; >> + }; >> + };