Re: [PATCH v1 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_v2()

["Heiko Stübner" <heiko@sntech.de>]

Hi Elaine,

Am Mittwoch, 15. Oktober 2025, 11:13:21 Mitteleuropäische Sommerzeit schrieb Elaine Zhang:
> The clock path of CPU may be simplified as follows:
> 
>     --gpll--|--\
>             |   \
>             |    \
>             |     \
>    --v0pll--| mux |--[gate]--[div]--clk_core--
>             |     /
>             |    /
>    --v1pll--|   /
>             |--/
> 

when introducing new core concepts, please really try to explain the
concept and also in detail why the old code cannot fullfill the new
requirements.

From what I gathered, the main difference is that on the bigger socs we
have one sort of dedicated PLL for each armclk (i.e. B0PLL, B1PLL, LPLL
on rk3588) with the other parents being used as an interim source while
we adjust the main one.

Here the rv1126b (and rk3506) don't have that, but instead can select
from a number of "equal-but-shared" PLL sources.

Is my reading correct here?


> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>  drivers/clk/rockchip/clk-cpu.c | 165 +++++++++++++++++++++++++++++++++
>  drivers/clk/rockchip/clk.c     |  24 +++++
>  drivers/clk/rockchip/clk.h     |  15 +++
>  3 files changed, 204 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
> index dcc9dcb597ae..a48628e5c095 100644
> --- a/drivers/clk/rockchip/clk-cpu.c
> +++ b/drivers/clk/rockchip/clk-cpu.c

[...]

> +struct clk *rockchip_clk_register_cpuclk_v2(const char *name,

can we please find a descriptive name instead of "_v2"

I guess if my reading above is correct something like "_multi_pll" or so
might be nice.


Thanks
Heiko