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Thu, 8 Aug 2024 02:49:40 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Aug 2024 02:49:40 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Aug 2024 02:49:40 -0500 Received: from [172.24.227.36] (a0497641-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [172.24.227.36] (may be forged)) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4787naki016627; Thu, 8 Aug 2024 02:49:36 -0500 Message-ID: <2279305f-2efa-4320-866a-fc4340d2e70c@ti.com> Date: Thu, 8 Aug 2024 13:19:35 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: ti: k3-am68-sk-base-board: Add clklb pin mux for mmc1 To: Bhavya Kapoor , , CC: , , , , , , , , References: <20240807101624.2713490-1-b-kapoor@ti.com> <8fa39624-9a92-404d-8651-9ade5700a7d3@ti.com> <1319a6ac-6784-45d6-8a0e-170e40d3aa18@ti.com> Content-Language: en-US From: Neha Malcom Francis In-Reply-To: <1319a6ac-6784-45d6-8a0e-170e40d3aa18@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi Bhavya On 08/08/24 13:08, Bhavya Kapoor wrote: > Hi Neha, > > On 08/08/24 11:51 am, Neha Malcom Francis wrote: >> Hi Bhavya >> >> On 07/08/24 15:46, Bhavya Kapoor wrote: >>> mmc1 was not functional since pin mux for clklb was not present. >>> Thus, add clklb pin mux to get MMC working. >>> >>> Fixes: a266c180b398 ("arm64: dts: ti: k3-am68-sk: Add support for AM68 SK >>> base board") >>> Signed-off-by: Bhavya Kapoor >>> --- >>> >>> rebased to next-20240807 >>> >>>   arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 + >>>   1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >>> b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >>> index 90dbe31c5b81..d5ceab79536c 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >>> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >>> @@ -204,6 +204,7 @@ main_mmc1_pins_default: main-mmc1-default-pins { >>>           pinctrl-single,pins = < >>>               J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ >>>               J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ >>> +            J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ >>>               J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ >>>               J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ >>>               J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ >> >> How is this different from the P23 pinmux for MMC1_CLK? Could you explain what >> CLKLB is, since it doesn't have a ball number I'm finding it difficult to >> understand what it is? >> > This pin needs to be setup so that MMC_CLK is looped back at pad level for > highspeed SDIO operations (has been same across K3 family). MMC0/1 has this pin > configured as INPUT by reset default as these have boot media > >  These pinmuxes are derived from pinmux file shared by EVM team during > wakeup/board bringup. > Thank you for explaining. Reviewed-by: Neha Malcom Francis > Regards > -- Thanking You Neha Malcom Francis