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AJvYcCWSgJVCzWh+/T3wR+mJimuWpF5gSLPHuP5rCQEOfgWmgNajuYv0Y63quojWJTMRni+EFbDQ+ovhLXmsT+1unRh1IRLTD1eabyOVOA== X-Gm-Message-State: AOJu0YyErtEqWMHDu3/s2libHg2pxZ1giQ/xZWn0K5hA4k9DtpaTIltC 1RXAYXQnavthajyewcHQ9Sol8ZYwUoK7R+HVQP8+oEac1Pus6wlJFNw/TpZ6JLs= X-Google-Smtp-Source: AGHT+IETxyB0snJNvMt9MaRxZtX7+j+x5oGjOWzm8oItSS/tUdUHCB4zwYBUxezahOThfFEGvBOjPA== X-Received: by 2002:a05:600c:6dca:b0:426:5269:983a with SMTP id 5b1f17b1804b1-426707cc00dmr43281485e9.8.1720621253364; Wed, 10 Jul 2024 07:20:53 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4266f6f07dasm83508525e9.12.2024.07.10.07.20.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Jul 2024 07:20:52 -0700 (PDT) Message-ID: <22db23bd-5872-49a0-990f-2a0e5f51bfb5@tuxon.dev> Date: Wed, 10 Jul 2024 17:20:50 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 09/12] i2c: riic: Add support for fast mode plus To: Geert Uytterhoeven Cc: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea References: <20240625121358.590547-1-claudiu.beznea.uj@bp.renesas.com> <20240625121358.590547-10-claudiu.beznea.uj@bp.renesas.com> From: claudiu beznea Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, Geert, all, On 28.06.2024 12:22, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Tue, Jun 25, 2024 at 2:14 PM Claudiu wrote: >> From: Claudiu Beznea >> >> Fast mode plus is available on most of the IP variants that RIIC driver >> is working with. The exception is (according to HW manuals of the SoCs >> where this IP is available) the Renesas RZ/A1H. For this, patch >> introduces the struct riic_of_data::fast_mode_plus. >> >> Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by >> instantiating the RIIC frequency to 1MHz and issuing i2c reads on the >> fast mode plus capable devices (and the i2c clock frequency was checked on >> RZ/G3S). >> >> Signed-off-by: Claudiu Beznea > > Thanks for your patch! > >> --- a/drivers/i2c/busses/i2c-riic.c >> +++ b/drivers/i2c/busses/i2c-riic.c >> @@ -407,6 +413,9 @@ static int riic_init_hw(struct riic_dev *riic) >> riic_writeb(riic, 0, RIIC_ICSER); >> riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3); >> >> + if (info->fast_mode_plus && t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) >> + riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER); > > Unless FM+ is specified, RIIC_ICFER is never written to. > Probably the register should always be initialized, also to make sure > the FMPE bit is cleared when it was set by the boot loader, but FM+ > is not to be used. Instead of clearing only this bit, what do you think about using reset_control_reset() instead of reset_control_deassert() in riic_i2c_probe()? HW manuals for all the devices listed in Documentation/devicetree/bindings/i2c/renesas,riic.yaml specifies that ICFER_FMPE register is initialized with a default value by reset. All the other registers are initialized with default values at reset (according to HW manuals). I've checked it on RZ/G3S and it behaves like this. With this: diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index ba969ad5f015..150e7841f178 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -457,7 +457,7 @@ static int riic_i2c_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(riic->rstc), "Error: missing reset ctrl\n"); - ret = reset_control_deassert(riic->rstc); + ret = reset_control_reset(riic->rstc); if (ret) return ret; I've did basic tests (i2cdetect + i2cget with FM+ frequency) on RZ/G2{L, LC, UL}, RZ/V2L and all was good. Thank you, Claudiu Beznea > > >> + >> riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); >> >> pm_runtime_mark_last_busy(dev); > > Gr{oetje,eeting}s, > > Geert >