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AJvYcCXJolbP5Vs7E/RlQngmUJu6EVsjAHg/JPUE4W8SSGEpM6zE6/UHP1eYZhh4AWlc0zA24/inTjyhcWJI@vger.kernel.org X-Gm-Message-State: AOJu0YxMN49e+c0cz3uVf0cB8YbaRC0j7xzNOas/sJMfD1+7TiLPhmbS 2g81qfnq8oL1epLZbt4KIln7X24Z0g6XXwHpckrW9p8X+jL4DS+PX+3So8rpDV8= X-Google-Smtp-Source: AGHT+IF0Dj116Hozge8v197MDvYjeTxK3MKp0aY5RS13PAtZvlLU8oqWjlPSuwRMds/rwKfYKaJo8g== X-Received: by 2002:a05:6602:15ca:b0:82d:d07:daaa with SMTP id ca18e2360f4ac-82d376b01c6mr102431939f.4.1726176646337; Thu, 12 Sep 2024 14:30:46 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d35f8dac37sm807546173.133.2024.09.12.14.30.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Sep 2024 14:30:45 -0700 (PDT) Message-ID: <22dd1d53-9ac5-4672-ad68-e82499038283@sifive.com> Date: Thu, 12 Sep 2024 16:30:43 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/5] mailbox: add Microchip IPC support To: Valentina Fernandez Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, peterlin@andestech.com, dminus@andestech.com, conor.dooley@microchip.com, conor+dt@kernel.org, ycliang@andestech.com, jassisinghbrar@gmail.com, robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, mathieu.poirier@linaro.org References: <20240912170025.455167-1-valentina.fernandezalanis@microchip.com> <20240912170025.455167-4-valentina.fernandezalanis@microchip.com> From: Samuel Holland Content-Language: en-US In-Reply-To: <20240912170025.455167-4-valentina.fernandezalanis@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Valentina, On 2024-09-12 12:00 PM, Valentina Fernandez wrote: > +static int mchp_ipc_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mchp_ipc_probe ipc_info; > + struct microchip_ipc *ipc; > + struct ipc_chan_info *priv; > + bool irq_avail = false; > + int ret; > + u32 chan_id; > + > + ret = sbi_probe_extension(SBI_EXT_MICROCHIP_TECHNOLOGY); > + if (ret <= 0) > + return dev_err_probe(dev, ret, "Microchip SBI extension not detected\n"); > + > + ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL); > + if (!ipc) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, ipc); > + > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(IPC_DMA_BIT_MASK)); > + if (ret) > + return dev_err_probe(dev, ret, "dma_set_mask_and_coherent failed\n"); > + > + ipc->buf_base = dmam_alloc_coherent(dev, sizeof(u32), &ipc->dma_addr, GFP_KERNEL); > + > + if (!ipc->buf_base) > + return -ENOMEM; One drive-by comment here: you don't need to use the DMA API to get a physical address for passing to the SBI interface. You can use __pa() on a kmalloc'd buffer, since kmalloc() returns memory from the linear map. This has the advantage of 1) using cacheable memory and 2) not rounding up the allocation size to a whole page. > + > + ret = mchp_ipc_sbi_send(SBI_EXT_IPC_PROBE, ipc->dma_addr); > + if (ret < 0) > + return dev_err_probe(dev, ret, "could not probe IPC SBI service\n"); > + > + memcpy(&ipc_info, ipc->buf_base, sizeof(struct mchp_ipc_probe)); Here sizeof(struct mchp_ipc_probe) > sizeof(u32), so if the DMA API wasn't rounding up the allocation size, this would be a buffer overflow. Regards, Samuel > + ipc->num_channels = ipc_info.num_channels; > + ipc->hw_type = ipc_info.hw_type; > + > + ipc->chans = devm_kcalloc(dev, ipc->num_channels, sizeof(*ipc->chans), GFP_KERNEL); > + if (!ipc->chans) > + return -ENOMEM; > + > + ipc->dev = dev; > + ipc->controller.txdone_irq = true; > + ipc->controller.dev = ipc->dev; > + ipc->controller.ops = &mchp_ipc_ops; > + ipc->controller.chans = ipc->chans; > + ipc->controller.num_chans = ipc->num_channels; > + ipc->controller.of_xlate = mchp_ipc_mbox_xlate; > + > + for (chan_id = 0; chan_id < ipc->num_channels; chan_id++) { > + priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + ipc->chans[chan_id].con_priv = priv; > + priv->id = chan_id; > + } > + > + if (ipc->hw_type == MIV_IHC) { > + ipc->cluster_cfg = devm_kcalloc(dev, num_online_cpus(), > + sizeof(struct mchp_ipc_cluster_cfg), > + GFP_KERNEL); > + if (!ipc->cluster_cfg) > + return -ENOMEM; > + > + if (mchp_ipc_get_cluster_aggr_irq(ipc)) > + irq_avail = true; > + } > + > + if (!irq_avail) > + return dev_err_probe(dev, -ENODEV, "missing interrupt property\n"); > + > + ret = devm_mbox_controller_register(dev, &ipc->controller); > + if (ret) > + return dev_err_probe(dev, ret, > + "Inter-Processor communication (IPC) registration failed\n"); > + > + return 0; > +}