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From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
	Dmitry Osipenko <digetx@gmail.com>,
	krzysztof.kozlowski@canonical.com, robh+dt@kernel.org,
	thierry.reding@gmail.com, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v5 1/4] memory: tegra: Add memory controller channels support
Date: Wed, 30 Mar 2022 02:48:11 +0300	[thread overview]
Message-ID: <22eb6b37-3bcd-71ab-f99f-dc059043b56b@collabora.com> (raw)
In-Reply-To: <981610f0-374a-b18f-8e3a-445b20edb257@nvidia.com>

On 3/25/22 07:50, Ashish Mhetre wrote:
> 
> 
> On 3/19/2022 9:12 PM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 16.03.2022 12:25, Ashish Mhetre пишет:
>>>  From tegra186 onwards, memory controller support multiple channels.
>>> Add support for mapping address spaces of these channels.
>>> Make sure that number of channels are as expected on each SOC.
>>> During error interrupts from memory controller, appropriate registers
>>> from these channels need to be accessed for logging error info.
>>>
>>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>>> ---
>>>   drivers/memory/tegra/mc.c       |  6 ++++
>>>   drivers/memory/tegra/tegra186.c | 52 +++++++++++++++++++++++++++++++++
>>>   drivers/memory/tegra/tegra194.c |  1 +
>>>   drivers/memory/tegra/tegra234.c |  1 +
>>>   include/soc/tegra/mc.h          |  7 +++++
>>>   5 files changed, 67 insertions(+)
>>>
>>> diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
>>> index bf3abb6d8354..3cda1d9ad32a 100644
>>> --- a/drivers/memory/tegra/mc.c
>>> +++ b/drivers/memory/tegra/mc.c
>>> @@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device
>>> *pdev)
>>>        if (IS_ERR(mc->regs))
>>>                return PTR_ERR(mc->regs);
>>>
>>> +     if (mc->soc->ops && mc->soc->ops->map_regs) {
>>> +             err = mc->soc->ops->map_regs(mc, pdev);
>>> +             if (err < 0)
>>> +                     return err;
>>> +     }
>>> +
>>>        mc->debugfs.root = debugfs_create_dir("mc", NULL);
>>>
>>>        if (mc->soc->ops && mc->soc->ops->probe) {
>>> diff --git a/drivers/memory/tegra/tegra186.c
>>> b/drivers/memory/tegra/tegra186.c
>>> index 3d153881abc1..a8a45e6ff1f1 100644
>>> --- a/drivers/memory/tegra/tegra186.c
>>> +++ b/drivers/memory/tegra/tegra186.c
>>> @@ -139,11 +139,62 @@ static int tegra186_mc_probe_device(struct
>>> tegra_mc *mc, struct device *dev)
>>>        return 0;
>>>   }
>>>
>>> +static int tegra186_mc_map_regs(struct tegra_mc *mc,
>>> +                             struct platform_device *pdev)
>>> +{
>>> +     struct device_node *np = pdev->dev.parent->of_node;
>>> +     int num_dt_channels, reg_cells = 0;
>>> +     struct resource *res;
>>> +     int i, ret;
>>> +     u32 val;
>>> +
>>> +     ret = of_property_read_u32(np, "#address-cells", &val);
>>> +     if (ret) {
>>> +             dev_err(&pdev->dev, "missing #address-cells property\n");
>>> +             return ret;
>>> +     }
>>> +
>>> +     reg_cells = val;
>>> +
>>> +     ret = of_property_read_u32(np, "#size-cells", &val);
>>> +     if (ret) {
>>> +             dev_err(&pdev->dev, "missing #size-cells property\n");
>>> +             return ret;
>>> +     }
>>> +
>>> +     reg_cells += val;
>>> +
>>> +     num_dt_channels =
>>> of_property_count_elems_of_size(pdev->dev.of_node, "reg",
>>> +                                                       reg_cells *
>>> sizeof(u32));
>>> +     /*
>>> +      * On tegra186 onwards, memory controller support multiple
>>> channels.
>>> +      * Apart from regular memory controller channels, there is one
>>> broadcast
>>> +      * channel and one for stream-id registers.
>>> +      */
>>> +     if (num_dt_channels < mc->soc->num_channels + 2) {
>>> +             dev_warn(&pdev->dev, "MC channels are missing, please
>>> update\n");
>>
>> Update what?
>>
>>> +             return 0;
>>> +     }
>>> +
>>> +     mc->mcb_regs = devm_platform_get_and_ioremap_resource(pdev, 1,
>>> &res);
>>
>> Can't we name each reg bank individually in the DT and then use
>> devm_platform_ioremap_resource_byname()?
>>
> That can be done but I think current logic will be better as we can
> simply ioremap them by running in loop and assigning the mc_regs array.
> Otherwise there will be like 17 ioremap_byname() individual calls for
> Tegra194 and Tegra234.
> Will it be fine having that many ioremap_byname() calls?
> Also, Tegra186 has 5 channels which are less than Tegra194 and Tegra234.
> If we go with ioremap_byname() then we'll have to differentiate number
> of ioremap_byname() calls.
for (i = 0; i < mc->soc->num_channels; i++) {
	sprintf(name, "mc%u", i);
	err = devm_platform_ioremap_resource_byname(dev, name);
	...
}

  reply	other threads:[~2022-03-29 23:48 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-16  9:25 [Patch v5 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-22 16:13     ` Ashish Mhetre
2022-03-25  4:50     ` Ashish Mhetre
2022-03-29 23:48       ` Dmitry Osipenko [this message]
2022-03-30  5:07         ` Ashish Mhetre
2022-03-20 12:31   ` Krzysztof Kozlowski
2022-03-22 18:04     ` Ashish Mhetre
2022-03-22 18:24       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-19 15:50   ` Dmitry Osipenko
2022-03-19 16:19     ` Dmitry Osipenko
2022-03-22 17:51       ` Ashish Mhetre
2022-03-22 16:48     ` Ashish Mhetre
2022-03-19 15:59   ` Dmitry Osipenko
2022-03-22 17:23     ` Ashish Mhetre
2022-03-29 23:51       ` Dmitry Osipenko
2022-03-30  5:02         ` Ashish Mhetre
2022-03-19 16:14   ` Dmitry Osipenko
2022-03-22 17:34     ` Ashish Mhetre
2022-03-30  0:01       ` Dmitry Osipenko
2022-03-30 10:16         ` Ashish Mhetre
2022-03-30 10:36           ` Dmitry Osipenko
2022-03-30 11:22             ` Ashish Mhetre
2022-03-31 19:49               ` Dmitry Osipenko
2022-03-31 21:55                 ` Ashish Mhetre
2022-03-20 12:53   ` Dmitry Osipenko
2022-03-23  8:36     ` Ashish Mhetre
2022-03-30  0:06   ` Dmitry Osipenko
2022-03-30  9:03     ` Ashish Mhetre
2022-03-30 10:19       ` Dmitry Osipenko
2022-03-30 10:34         ` Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-20  2:13   ` Rob Herring
2022-03-20 12:42   ` Krzysztof Kozlowski
2022-03-22 18:12     ` Ashish Mhetre
2022-03-22 18:42       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre

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