From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B757C43334 for ; Mon, 20 Jun 2022 11:24:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241213AbiFTLY3 (ORCPT ); Mon, 20 Jun 2022 07:24:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229910AbiFTLY0 (ORCPT ); Mon, 20 Jun 2022 07:24:26 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43B2615A30 for ; Mon, 20 Jun 2022 04:24:23 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id cf14so4890522edb.8 for ; Mon, 20 Jun 2022 04:24:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=7YbItpgX2LBuNx7lKZqosV1saRLcfoQOlviZpKCZMRM=; b=T1nbdeKFeraRecCd3Hn8u72fu7OtLH6DrLq5ON5gSmWupN8DmcewNuz4ssWpaI6Xr3 00ouvgo7T/iJfHEVzPbvCwzkVVC/FLD1F1VGObB6fhPWw8Z8ifaa7TJ1DbhA2jwSbvAL aMdd8ALj7hUvi3l0A8irE1JpXZ/LCYWWt4RDZ6IDBSakoQBhyBwmg84IbDt2f4kc3YP8 FCIZps2S9S0/gun+pdnVlHrVXBxtOymYPB9Cp8hvq77lzgg4ncnndNWRtCy+H3PQVrrZ Nw+FUqRkquAcSwohuCdkIlMDoPCJ1KVupWwXmfxUgyUdz92JTE42DYq1e0dfYtT6lwPe tBHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=7YbItpgX2LBuNx7lKZqosV1saRLcfoQOlviZpKCZMRM=; b=v9KvJJJbHStGGoToES10IsJa89ezg/b7JtnhDngP8FIXHrOake2KDyEH1jpdOBmE5M Z/frNQNA/EAsdborMRMYKJVy5oVCufPNfLebhkIwk82FGvkgYRURTqu9kqUgU6Cqxip6 Hfr3FrU4urqJRPvYJa2YpEM3YxXbLAnMRy/NHytnNq6LQXk3O7ayACAoQCEaQrx7hVac j+SyctsEbmkrTAf4qkGLAw8TRlwz80UMemSR0kTyacNoL4G5xKj8o7UUo0jri9NuuJ0y GxvJjmp5c81TSYjR74FhneRYK6JOi9ujtuIhQoe5bdB1e5FPEAFM8k1LPLuRMTFCUBRS b8eQ== X-Gm-Message-State: AJIora/BbpoVAiPD0MSKjdWjUYFERVJQy7/JNUGC8Xyv1Q+PXMUkLy4d +3g0PeY9l2ysmguCDtmG0mWXdQ== X-Google-Smtp-Source: AGRyM1vlX+1cAORRQeoyJ5GjVZ99zgy5FGMZ5N3PChpplc/Pk3QKA+jkysUom51C8/8Xy+I1QI/eXw== X-Received: by 2002:a05:6402:40c6:b0:42f:9ff8:62f8 with SMTP id z6-20020a05640240c600b0042f9ff862f8mr28458343edb.95.1655724261713; Mon, 20 Jun 2022 04:24:21 -0700 (PDT) Received: from [192.168.0.209] (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id 15-20020a170906300f00b006f3ef214dd9sm5832791ejz.63.2022.06.20.04.24.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jun 2022 04:24:19 -0700 (PDT) Message-ID: <22f4ba43-2505-3000-24b6-b01d58d87e7f@linaro.org> Date: Mon, 20 Jun 2022 13:24:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 3/4] arm64: dts: qcom: msm8996: add GCC's optional clock sources Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20220620071936.1558906-1-dmitry.baryshkov@linaro.org> <20220620071936.1558906-4-dmitry.baryshkov@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20220620071936.1558906-4-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 20/06/2022 09:19, Dmitry Baryshkov wrote: > Add missing GCC clock sources. This includes PCIe and USB PIPE and UFS > symbol clocks. > > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index e97f193aefd3..6c7380f86383 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -689,8 +689,22 @@ gcc: clock-controller@300000 { > > clocks = <&rpmcc RPM_SMD_BB_CLK1>, > <&rpmcc RPM_SMD_LN_BB_CLK>, > - <&sleep_clk>; > - clock-names = "cxo", "cxo2", "sleep_clk"; > + <&sleep_clk>, > + <&pciephy_0>, > + <&pciephy_1>, > + <&pciephy_2>, > + <&ssusb_phy_0>, > + <0>, <0>, <0>; Since the clocks are optional, there is no need to pass <0> to them. I think it does not bring any benefits. > + clock-names = "cxo", > + "cxo2", > + "sleep_clk", > + "pcie_0_pipe_clk_src", > + "pcie_1_pipe_clk_src", > + "pcie_2_pipe_clk_src", > + "usb3_phy_pipe_clk_src", > + "ufs_rx_symbol_0_clk_src", > + "ufs_rx_symbol_1_clk_src", > + "ufs_tx_symbol_0_clk_src"; > }; > > tsens0: thermal-sensor@4a9000 { Best regards, Krzysztof