From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 632ECC433F5 for ; Thu, 12 May 2022 12:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353019AbiELMmy (ORCPT ); Thu, 12 May 2022 08:42:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348607AbiELMmx (ORCPT ); Thu, 12 May 2022 08:42:53 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6980166FA3; Thu, 12 May 2022 05:42:50 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1np89T-00025a-Rp; Thu, 12 May 2022 14:42:43 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Atish Patra , linux-riscv@lists.infradead.org Cc: "linux-kernel@vger.kernel.org List" , Albert Ou , Atish Patra , Damien Le Moal , DTML , Jisheng Zhang , Krzysztof Kozlowski , linux-riscv , Palmer Dabbelt , Paul Walmsley , Rob Herring , Anup Patel Subject: Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32 Date: Thu, 12 May 2022 14:42:42 +0200 Message-ID: <23274575.ouqheUzb2q@diego> In-Reply-To: References: <20220511201107.2311757-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel: > On Thu, May 12, 2022 at 1:41 AM Atish Patra wrote: > > > > Pass the upper half of the initial value of the counter correctly > > for RV32. > > > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > > > > Signed-off-by: Atish Patra > > --- > > drivers/perf/riscv_pmu_sbi.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > index a1317a483512..24cea59612be 100644 > > --- a/drivers/perf/riscv_pmu_sbi.c > > +++ b/drivers/perf/riscv_pmu_sbi.c > > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, > > max_period = riscv_pmu_ctr_get_width_mask(event); > > init_val = local64_read(&hwc->prev_count) & max_period; > > sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, > > - flag, init_val, 0, 0); > > + flag, init_val, init_val >> 32, 0); > > This should be under "#if __riscv_xlen == 32". What's the difference between using CONFIG_32BIT and checking the __riscv_xlen flag value? CONFIG_32BIT seems to be a bit the more kernel'ish way to do this, but it looks like most SBI parts check the __riscv_xlen instead. In any case, looking at the opensbi-side of the call, this fix is abviously correct, so Reviewed-by: Heiko Stuebner