From: "Heiko Stübner" <heiko@sntech.de>
To: Jisheng Zhang <jszhang@kernel.org>, Conor Dooley <conor@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>
Subject: Re: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree
Date: Mon, 08 May 2023 19:09:20 +0200 [thread overview]
Message-ID: <2344188.NG923GbCHz@diego> (raw)
In-Reply-To: <20230508-unmoved-unvocal-9a6c5fc0c629@spud>
Am Montag, 8. Mai 2023, 18:44:04 CEST schrieb Conor Dooley:
> On Tue, May 09, 2023 at 12:26:10AM +0800, Jisheng Zhang wrote:
> > On Sun, May 07, 2023 at 10:35:12PM +0100, Conor Dooley wrote:
> > > On Mon, May 08, 2023 at 02:23:02AM +0800, Jisheng Zhang wrote:
> > >
> > > > + c910_0: cpu@0 {
> > > > + compatible = "thead,c910", "riscv";
> > > > + device_type = "cpu";
> > > > + riscv,isa = "rv64imafdc";
> > >
> > > Does this support more than "rv64imafdc"?
> > > I assume there's some _xtheadfoo extensions that it does support,
> > > although I am not sure how we are proceeding with those - Heiko might
> > > have a more nuanced take.
> > >
> > > > + reset: reset-sample {
> > > > + compatible = "thead,reset-sample";
> > >
> > > What is a "reset-sample"?
> >
> > This node is only for opensbi. The compatible string is already in
> > opensbi. Do we also need to add dt-binding for it in linux?
>
> If it's to be included in the kernel's dts, then yes, you do need a
> dt-binding. If you remove it, then you don't :)
>
> That said, "thead,reset-sample" is a strangely named compatible, so if
> you do keep it it may end up needing a rename!
and you'll need to justify that this describes actual hardware
(dt-maintainers iterate all the time that dt is a hardware description, not
a configuration scheme).
The question also would be if this is part of upstream opensbi at all.
In general though, openSBI does something similar with their perf-counter
description. Describing the mapping and eventids usable in which counter
via a structure passed from u-boot to openSBI.
The difference here is, that openSBI then removes the relevant nodes from
the dt, so that the kernel never sees them [0] .
As you reset-sample seems to fall into a similar category, I guess
it would be better suited in an a foo-u-boot.dtsi ?
[0] https://github.com/riscv-software-src/opensbi/blob/master/lib/utils/fdt/fdt_pmu.c#L42
next prev parent reply other threads:[~2023-05-08 17:09 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-07 18:22 [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-07 18:23 ` [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Jisheng Zhang
2023-05-07 21:18 ` Conor Dooley
2023-05-08 3:14 ` Icenowy Zheng
2023-05-08 6:52 ` Guo Ren
2023-05-08 7:07 ` Conor Dooley
2023-05-08 16:09 ` Jisheng Zhang
2023-05-08 9:17 ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-07 21:22 ` Conor Dooley
2023-05-08 6:42 ` Guo Ren
2023-05-08 6:52 ` Conor Dooley
2023-05-08 6:58 ` Guo Ren
2023-05-08 7:04 ` Conor Dooley
2023-05-07 18:23 ` [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Jisheng Zhang
2023-05-07 21:35 ` Conor Dooley
2023-05-08 3:32 ` Icenowy Zheng
2023-05-08 7:01 ` Conor Dooley
2023-05-08 8:23 ` Heiko Stübner
2023-05-08 8:35 ` Conor Dooley
2023-05-08 15:56 ` Heiko Stübner
2023-05-08 16:26 ` Jisheng Zhang
2023-05-08 16:44 ` Conor Dooley
2023-05-08 17:09 ` Heiko Stübner [this message]
2023-05-21 15:37 ` Guo Ren
2023-05-21 17:08 ` Conor Dooley
2023-05-22 1:36 ` Guo Ren
2023-05-08 9:20 ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-05-07 21:27 ` Conor Dooley
2023-05-08 6:44 ` Guo Ren
2023-05-07 18:23 ` [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-07 21:21 ` Conor Dooley
2023-05-08 16:17 ` Jisheng Zhang
2023-05-08 17:23 ` Conor Dooley
2023-05-08 6:22 ` Guo Ren
2023-05-08 6:16 ` [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Guo Ren
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