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a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1730983793; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=rVq9b6pcFOHREaNN9fex606hOk1inbkqT9uhtMs6aJA=; b=OvymNaxWbHJgVj9vxdqQ3uuum2UfzC+CLSQ4JBH6IvTuTH3US6xD+qIv0XOF+o/LtsLBHk 4xmrj5mW0Patp4egGwKF94z9YzISIS6JSBZvEaepmEaHbScQ6pQA6kYoUDjQHu1Z1tZWSV WGhp4dOkHMPiOsoTSIpeOUW2W1RfAdzLT8ERF8XRAShA1A4J94+TfaSEs8bp6GqvuKsfV4 CFRhysC0O0JzhXJY5oGI38zGYyz/eUsGZkVsHdgNQEzDe0y8kdVWwvTV12HCuWtWh7D3w9 D6PmzK9QdSH9RqRtdLTInBw4/J2dm8xY+x2avdzr8Pe1sBjdm9ENQRULKPTDiA== From: Alexander Stein To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, Pengfei Li Cc: joao.goncalves@toradex.com, frieder.schrempf@kontron.de, marex@denx.de, hvilleneuve@dimonoff.com, peng.fan@nxp.com, m.othacehe@gmail.com, mwalle@kernel.org, Max.Merchel@ew.tq-group.com, hiago.franco@toradex.com, tharvey@gateworks.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, ping.bai@nxp.com, ye.li@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Subject: Re: [PATCH 2/3] arm64: dts: freescale: Add i.MX91 dtsi support Date: Thu, 07 Nov 2024 13:49:50 +0100 Message-ID: <2350046.ElGaqSPkdT@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20241108022703.1877171-3-pengfei.li_1@nxp.com> References: <20241108022703.1877171-1-pengfei.li_1@nxp.com> <20241108022703.1877171-3-pengfei.li_1@nxp.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Last-TLS-Session-Version: TLSv1.3 Hi, thanks for putting me on CC. Am Freitag, 8. November 2024, 03:27:02 CET schrieb Pengfei Li: > The i.MX 91 family features an Arm Cortex-A55 running at up to > 1.4GHz, support for modern LPDDR4 memory to enable platform longevity, > along with a rich set of peripherals targeting medical, industrial > and consumer IoT market segments. >=20 > The design of the i.MX91 platform is very similar to i.MX93. > The mainly difference between i.MX91 and i.MX93 is as follows: > - i.MX91 removed some clocks and modified the names of some clocks. > - i.MX91 only has one A core >=20 > Signed-off-by: Pengfei Li > Reviewed-by: Frank Li > --- > arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx91.dtsi | 66 ++ > 2 files changed, 836 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h > create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi >=20 > diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/b= oot/dts/freescale/imx91-pinfunc.h > new file mode 100644 > index 000000000000..bc58ce2102b2 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h =46WIW this is a 1:1 copy from downstream kernel > diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/d= ts/freescale/imx91.dtsi > new file mode 100644 > index 000000000000..a9f4c1fe61cc > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi > @@ -0,0 +1,66 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2024 NXP > + */ > + > +#include "imx91-pinfunc.h" > +#include "imx93.dtsi" > + > +&{/thermal-zones/cpu-thermal/cooling-maps/map0} { > + cooling-device =3D > + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > +}; > + > +&clk { > + compatible =3D "fsl,imx91-ccm"; > +}; > + > +&eqos { > + clocks =3D <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, > + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, > + <&clk IMX91_CLK_ENET_TIMER>, > + <&clk IMX91_CLK_ENET1_QOS_TSN>, > + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; > + assigned-clocks =3D <&clk IMX91_CLK_ENET_TIMER>, > + <&clk IMX91_CLK_ENET1_QOS_TSN>; > + assigned-clock-parents =3D <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, > + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; Is it just me or is the alignment of new lines not matching? > +}; > + > +&fec { > + clocks =3D <&clk IMX91_CLK_ENET2_REGULAR_GATE>, > + <&clk IMX91_CLK_ENET2_REGULAR_GATE>, > + <&clk IMX91_CLK_ENET_TIMER>, > + <&clk IMX91_CLK_ENET2_REGULAR>, > + <&clk IMX93_CLK_DUMMY>; > + assigned-clocks =3D <&clk IMX91_CLK_ENET_TIMER>, > + <&clk IMX91_CLK_ENET2_REGULAR>; > + assigned-clock-parents =3D <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, > + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; Here as well: Is it just me or is the alignment of new lines not matching? > + assigned-clock-rates =3D <100000000>, <250000000>; > +}; > + > +&i3c1 { > + clocks =3D <&clk IMX93_CLK_BUS_AON>, > + <&clk IMX93_CLK_I3C1_GATE>, > + <&clk IMX93_CLK_DUMMY>; > +}; > + > +&i3c2 { > + clocks =3D <&clk IMX93_CLK_BUS_WAKEUP>, > + <&clk IMX93_CLK_I3C2_GATE>, > + <&clk IMX93_CLK_DUMMY>; > +}; > + > +&tmu { > + status =3D "disabled"; Why does the TMU needs to be disabled instead of deleted? > +}; > + > +/* i.MX91 only has one A core */ > +/delete-node/ &A55_1; > + > +/* i.MX91 not has cm33 */ > +/delete-node/ &cm33; > + > +/* i.MX91 not has power-domain@44461800 */ > +/delete-node/ &mlmix; >=20 Shouldn't the following node also be removed? * mipi_csi * dsi * lvds_bridge * lcdif_to_dsi * lcdif_to_ldb Also in downstream kernel IMX91_CLK_MEDIA_AXI, which is IMX93_CLK_MEDIA_AXI upstream, is set to 200 MHz. Is this applicable here as well? Best regards, Alexander =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/