From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 879D214A615; Wed, 19 Jun 2024 15:35:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718811332; cv=none; b=HHC5nU5Rzw+SOD65JEtAamFa+IT9PEtSacTjpS86XtrZ3OA3qhY/3riGMSX7AwiUL36a2ay98Vd6oNpUSkyeMFHB3z6B30XCccCTfAXclUUyYDeS9fw/mU780blxOPSICfI6tERCShho/NnLoO9wnfgq6M933e0NrnB99LuKtf0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718811332; c=relaxed/simple; bh=BPtgPXEQiiuawM/+sV4u73JRNY2yrOfHMDvL02Wxe9U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OVgnsopiJKVGgopJg5FnNmDWrhA/JjEQJiP4ai+eMBkIh2R3vVK7ai1E1jviBSiJ8mb0ZW74XfiDI4uEsnWEYDOL9dhc7thVcEz6mLaNdhkwhMQnfkdrRCDHmBqeu+2mtaAEDkeY3Ira00JLg21xau6JspYqnpbm4brBqNc9UTU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e8616dc.versanet.de ([94.134.22.220] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sJxL1-00061d-Ji; Wed, 19 Jun 2024 17:35:07 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-kernel@vger.kernel.org, Detlev Casanova Cc: Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Sebastian Reichel , Dragan Simic , Diederik de Haas , Andy Yan , Boris Brezillon , Hans Verkuil , Daniel Almeida , Paul Kocialkowski , Nicolas Dufresne , Benjamin Gaignard , Jonas Karlman , Alex Bee , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-staging@lists.linux.dev, Detlev Casanova Subject: Re: [PATCH v2 4/4] arm64: dts: rockchip: Add rkvdec2 Video Decoder on rk3588(s) Date: Wed, 19 Jun 2024 17:34:51 +0200 Message-ID: <2379859.OYXXYNVTWy@diego> In-Reply-To: <20240619150029.59730-5-detlev.casanova@collabora.com> References: <20240619150029.59730-1-detlev.casanova@collabora.com> <20240619150029.59730-5-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Am Mittwoch, 19. Juni 2024, 16:57:21 CEST schrieb Detlev Casanova: > Add the rkvdec2 Video Decoder to the RK3588s devicetree. > > Signed-off-by: Detlev Casanova > --- > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 50 +++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > index 6ac5ac8b48ab..7690632f57f1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > @@ -2596,6 +2596,16 @@ system_sram2: sram@ff001000 { > ranges = <0x0 0x0 0xff001000 0xef000>; > #address-cells = <1>; > #size-cells = <1>; > + > + vdec0_sram: rkvdec-sram@0 { > + reg = <0x0 0x78000>; > + pool; > + }; > + > + vdec1_sram: rkvdec-sram@1 { > + reg = <0x78000 0x77000>; > + pool; > + }; > }; > > pinctrl: pinctrl { > @@ -2665,6 +2675,46 @@ gpio4: gpio@fec50000 { > #interrupt-cells = <2>; > }; > }; > + > + vdec0: video-decoder@fdc38100 { > + compatible = "rockchip,rk3588-vdec"; > + reg = <0x0 0xfdc38100 0x0 0x500>; > + interrupts = ; > + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, > + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; > + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; > + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, > + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; > + assigned-clock-rates = <800000000>, <600000000>, > + <600000000>, <1000000000>; > + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, > + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; > + reset-names = "rst_axi", "rst_ahb", "rst_cabac", > + "rst_core", "rst_hevc_cabac"; > + power-domains = <&power RK3588_PD_RKVDEC0>; > + sram = <&vdec0_sram>; > + status = "okay"; okay is the default status, so is not needed when the node is always-on > + }; > + > + vdec1: video-decoder@fdc40100 { > + compatible = "rockchip,rk3588-vdec"; > + reg = <0x0 0xfdc40100 0x0 0x500>; > + interrupts = ; > + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, > + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; > + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; > + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, > + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; > + assigned-clock-rates = <800000000>, <600000000>, > + <600000000>, <1000000000>; > + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, > + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; > + reset-names = "rst_axi", "rst_ahb", "rst_cabac", > + "rst_core", "rst_hevc_cabac"; > + power-domains = <&power RK3588_PD_RKVDEC1>; > + sram = <&vdec1_sram>; > + status = "okay"; same > + }; > }; > > #include "rk3588s-pinctrl.dtsi" >