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Tue, 2 Dec 2025 12:48:15 +0100 (CET) From: Alexander Stein To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, frank.li@nxp.com, Sherry Sun Cc: devicetree@vger.kernel.org, kernel@pengutronix.de, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart Date: Tue, 02 Dec 2025 12:48:15 +0100 Message-ID: <2395053.ElGaqSPkdT@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20251202111638.3553-1-sherry.sun@nxp.com> References: <20251202111638.3553-1-sherry.sun@nxp.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-cloud-security-sender:alexander.stein@ew.tq-group.com X-cloud-security-recipient:devicetree@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: alexander.stein@ew.tq-group.com X-cloud-security-Mailarchivtype:outbound X-cloud-security-Virusscan:CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay90-hz2.antispameurope.com with 4dLJtm3MJzzWycw X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest:199991314bca0e7504113f70cfa02bc4 X-cloud-security:scantime:1.766 DKIM-Signature: a=rsa-sha256; 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Dezember 2025, 12:16:38 CET schrieb Sherry Sun: > The commit 616effc0272b5 ("arm64: dts: imx8: Fix lpuart DMA channel > order") swap uart rx and tx channel at common imx8-ss-dma.dtsi. But miss > update imx8qm-ss-dma.dtsi. >=20 > The commit 5a8e9b022e569 ("arm64: dts: imx8qm-ss-dma: Pass lpuart > dma-names") just simple add dma-names as binding doc requirement. >=20 > Correct lpuart0 - lpuart3 dma rx and tx channels, and use defines for > the FSL_EDMA_RX flag. >=20 > Fixes: 616effc0272b5 ("arm64: dts: imx8: Fix lpuart DMA channel order") I'm wondering if this is actually a fix for 5a8e9b022e569 ("arm64: dts: imx8qm-ss-dma: Pass lpuart dma-names") instead. 616effc0272b5 just focuses on the common parts. But I don't have a strong opinion here. Thanks and best regards, Alexander > Signed-off-by: Sherry Sun > --- > arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) >=20 > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8qm-ss-dma.dtsi > index 5f24850bf322..974e193f8dcb 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi > @@ -172,25 +172,25 @@ &flexcan3 { > =20 > &lpuart0 { > compatible =3D "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; > - dmas =3D <&edma2 13 0 0>, <&edma2 12 0 1>; > + dmas =3D <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; > dma-names =3D "rx","tx"; > }; > =20 > &lpuart1 { > compatible =3D "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; > - dmas =3D <&edma2 15 0 0>, <&edma2 14 0 1>; > + dmas =3D <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; > dma-names =3D "rx","tx"; > }; > =20 > &lpuart2 { > compatible =3D "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; > - dmas =3D <&edma2 17 0 0>, <&edma2 16 0 1>; > + dmas =3D <&edma2 16 0 FSL_EDMA_RX>, <&edma2 17 0 0>; > dma-names =3D "rx","tx"; > }; > =20 > &lpuart3 { > compatible =3D "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; > - dmas =3D <&edma2 19 0 0>, <&edma2 18 0 1>; > + dmas =3D <&edma2 18 0 FSL_EDMA_RX>, <&edma2 19 0 0>; > dma-names =3D "rx","tx"; > }; > =20 >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/