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AJvYcCUB5pwzyoSclYDTI5QYU3deeZrgzUGqMwgi5o3tm2gB20a/L+UDExOyfIHdGGtFoSsIG7MrL7i8MzNt@vger.kernel.org X-Gm-Message-State: AOJu0Yz9hC+Idt4e0wJ8JZ7t1VLJiNK42YAziF1GKqGzREj3bu59cnSi B/Cfgy9XNtJpX90bILVi2K/uqPaWGwPIeFtGh6F5ks5wqBhPDl4kRhREWfzoLuQ= X-Gm-Gg: ASbGncuGO12gcV1TV1R2VCszBR1Zgjsi7jwo7kvgBWqGIdaIqUXIz+H0ccKq0DDLypK pBo/2taZqNgU+eTRfmvU9gDLfaZiElgcDMIjACpSF7E/Uft71oIJKzJcLVNplDeKgrcwGHOG1kx qhx2XTMe91pxc/rVkyRP2T3tt8uMCiED1LFbmHOKPQSsSmow1PhD/heNdEKTw7e1Swi6Wg8ERyi r4qQa1BCy7YlnWC8ZaOKzasTwMFDY0Gl6wLkr2KOHmhSuFVxJnQxyfBFJ4= X-Google-Smtp-Source: AGHT+IGUfN/EA4JH6RTVsbnUKthIOhG2zwFRZUFAX7rqRG2CHXvmm33MqQPTkWqeEZrSe9CBG7Ax8g== X-Received: by 2002:a05:600c:4e88:b0:434:fddf:5c0c with SMTP id 5b1f17b1804b1-434fff30e74mr2642745e9.4.1733746234205; Mon, 09 Dec 2024 04:10:34 -0800 (PST) Received: from [192.168.50.4] ([82.78.167.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434e8bb0390sm86199035e9.27.2024.12.09.04.10.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Dec 2024 04:10:33 -0800 (PST) Message-ID: <240a461f-9c46-4f02-81f9-b2c7453fa1f4@tuxon.dev> Date: Mon, 9 Dec 2024 14:10:31 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/8] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches Content-Language: en-US To: Geert Uytterhoeven Cc: magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, lethal@linux-sh.org, g.liakhovetski@gmx.de, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, Claudiu Beznea References: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> <20241115134401.3893008-7-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, Geert, On 09.12.2024 12:09, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Fri, Nov 15, 2024 at 2:50 PM Claudiu wrote: >> From: Claudiu Beznea >> >> There are different switches available on both the RZ/G3S SMARC Module and >> RZ SMARC Carrier II boards. These switches are used to route different SoC >> signals to different parts available on board. >> >> These switches are described in device trees through macros. These macros >> are set accordingly such that the resulted compiled dtb to describe the >> on-board switches states. >> >> Based on the SW_CONFIG3 switch state (populated on the module board), the >> SCIF3 SoC interface is routed or not to an U(S)ART pin header available on >> the carrier board. As the SCIF3 is accessible through the carrier board, >> the device tree enables it in the carrier DTS. To be able to cope with >> these type of configurations, add a header file where all the on-board >> switches can be described and shared accordingly between module and carrier >> board. >> >> Commit prepares the code to enable SCIF3 on the RZ/G3S carrier device >> tree. >> >> Signed-off-by: Claudiu Beznea > > Thanks for your patch! > >> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi >> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi >> @@ -9,25 +9,7 @@ >> #include >> #include >> >> -/* >> - * On-board switches' states: >> - * @SW_OFF: switch's state is OFF >> - * @SW_ON: switch's state is ON >> - */ >> -#define SW_OFF 0 >> -#define SW_ON 1 >> - >> -/* >> - * SW_CONFIG[x] switches' states: >> - * @SW_CONFIG2: >> - * SW_OFF - SD0 is connected to eMMC >> - * SW_ON - SD0 is connected to uSD0 card >> - * @SW_CONFIG3: >> - * SW_OFF - SD2 is connected to SoC >> - * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC >> - */ >> -#define SW_CONFIG2 SW_OFF >> -#define SW_CONFIG3 SW_ON >> +#include "rzg3s-smarc-switches.h" >> >> / { >> compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; >> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h >> new file mode 100644 >> index 000000000000..e2d9b953f627 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h >> @@ -0,0 +1,32 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ > > I agree with Rob about the license. > >> +/* >> + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II >> + * boards. >> + * >> + * Copyright (C) 2024 Renesas Electronics Corp. >> + */ >> + >> +#ifndef __RZG3S_SMARC_SWITCHES__ >> +#define __RZG3S_SMARC_SWITCHES__ >> + >> +/* >> + * On-board switches' states: >> + * @SW_OFF: switch's state is OFF >> + * @SW_ON: switch's state is ON >> + */ >> +#define SW_OFF 0 >> +#define SW_ON 1 >> + >> +/* >> + * SW_CONFIG[x] switches' states: >> + * @SW_CONFIG2: >> + * SW_OFF - SD0 is connected to eMMC >> + * SW_ON - SD0 is connected to uSD0 card >> + * @SW_CONFIG3: >> + * SW_OFF - SD2 is connected to SoC >> + * SW_ON - SCIF3, SSI3, IRQ0, IRQ1 connected to SoC > > Note that the original comment above says "SCIF1, SSI0", and looking > at the schematics (IC7 and IC8 controlled by SW_SD2_EN#), that is > actually correct? You're right, I'm not sure why I've changed it. I'll fix it in the next version. Thank you for your review, Claudiu > >> + */ >> +#define SW_CONFIG2 SW_OFF >> +#define SW_CONFIG3 SW_ON >> + >> +#endif /* __RZG3S_SMARC_SWITCHES__ */ > > Gr{oetje,eeting}s, > > Geert >