Re: [PATCH] Documentation/devicetree: document OCTEON USB bindings

[Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>]

On Tuesday 05 May 2015 20:57:52 Aaro Koskinen wrote:
> 
> On Tue, May 05, 2015 at 12:02:04PM +0200, Arnd Bergmann wrote:
> > What does that main node actually do?
> > 
> > The common setup is that you have regular ehci/ohci/uhci host bridges
> > connected to an mmio bus, plus with shared PHY driver that would nowadays
> > sit in drivers/phy/ and handle the setup of the physical USB interface.
> 
> The main node is not just PHY and clock control, there is also DMA
> registers at least. Also the controller part is not generic ?hci.

Are you sure it's not one of the other common host implementations
(synopsys dwc2, mentor musb, chipidea, ...) then? Maybe there is
already a binding.

If not, would it make sense to put the two nodes into one that is
just handled by a single driver?

> > Is Octeon different from everything else here?
> 
> Certainly it's not like any generic COTS PC HW...

I was asking about SoC implementations like the octeon-6335, 
which seems to be more regular.

	Arnd
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