[PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC

[PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC

[Kevin Chen]

This patchset adds initial support for the ASPEED.
AST27XX Board Management controller (BMC) SoC family.

AST2700 is ASPEED's 8th-generation server management processor.
Featuring a quad-core ARM Cortex A35 64-bit processor and two
independent ARM Cortex M4 processors

This patchset adds minimal architecture and drivers such as:
Clocksource, Clock and Reset

This patchset was tested on the ASPEED AST2700 evaluation board.

Kevin Chen (10):
  dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700
    SCU
  dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock
  clk: ast2700: add clock controller
  dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset
  dt-bindings: arm: aspeed: Add maintainer
  dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string
  arm64: aspeed: Add support for ASPEED AST2700 BMC SoC
  arm64: dts: aspeed: Add initial AST27XX device tree
  arm64: dts: aspeed: Add initial AST2700 EVB device tree
  arm64: defconfig: Add ASPEED AST2700 family support

 .../bindings/arm/aspeed/aspeed.yaml           |    6 +
 .../bindings/mfd/aspeed,ast2x00-scu.yaml      |    3 +
 MAINTAINERS                                   |    3 +
 arch/arm64/Kconfig.platforms                  |   14 +
 arch/arm64/boot/dts/Makefile                  |    1 +
 arch/arm64/boot/dts/aspeed/Makefile           |    4 +
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     |  217 +++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |   50 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/clk-ast2700.c                     | 1166 +++++++++++++++++
 .../dt-bindings/clock/aspeed,ast2700-clk.h    |  180 +++
 .../dt-bindings/reset/aspeed,ast2700-reset.h  |  126 ++
 13 files changed, 1772 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
 create mode 100644 drivers/clk/clk-ast2700.c
 create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
 create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h

-- 
2.34.1

[PATCH v1 01/10] dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU

[Kevin Chen]

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
index 86ee69c0f45b..3fc991e4514d 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
@@ -13,6 +13,7 @@ description:
 maintainers:
   - Joel Stanley <joel@jms.id.au>
   - Andrew Jeffery <andrew@aj.id.au>
+  - Kevin Chen <kevin_chen@aspeedtech.com>
 
 properties:
   compatible:
@@ -21,6 +22,7 @@ properties:
           - aspeed,ast2400-scu
           - aspeed,ast2500-scu
           - aspeed,ast2600-scu
+          - aspeed,ast2700-scu
       - const: syscon
       - const: simple-mfd
 
@@ -76,6 +78,7 @@ patternProperties:
               - aspeed,ast2400-silicon-id
               - aspeed,ast2500-silicon-id
               - aspeed,ast2600-silicon-id
+              - aspeed,ast2700-silicon-id
           - const: aspeed,silicon-id
 
       reg:
-- 
2.34.1

[PATCH v1 02/10] dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock

[Kevin Chen]

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 .../dt-bindings/clock/aspeed,ast2700-clk.h    | 180 ++++++++++++++++++
 1 file changed, 180 insertions(+)
 create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h

diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h b/include/dt-bindings/clock/aspeed,ast2700-clk.h
new file mode 100644
index 000000000000..5ca85503736d
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 clock controller.
+ *
+ * Copyright (c) 2023 Aspeed Technology Inc.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_AST2700_H
+#define __DT_BINDINGS_CLOCK_AST2700_H
+
+/* SOC0 clk-gate */
+#define SCU0_CLK_GATE_MCLK	(0)
+#define SCU0_CLK_GATE_ECLK	(1)
+#define SCU0_CLK_GATE_GCLK	(2)
+#define SCU0_CLK_GATE_VCLK	(3)
+#define SCU0_CLK_GATE_BCLK	(4)
+#define SCU0_CLK_GATE_D1CLK	(5)
+#define SCU0_CLK_GATE_REFCLK	(6)
+#define SCU0_CLK_GATE_USB0CLK	(7)
+#define SCU0_CLK_GATE_RSV8	(8)
+#define SCU0_CLK_GATE_USB1CLK	(9)
+#define SCU0_CLK_GATE_D2CLK	(10)
+#define SCU0_CLK_GATE_RSV11	(11)
+#define SCU0_CLK_GATE_RSV12	(12)
+#define SCU0_CLK_GATE_YCLK	(13)
+#define SCU0_CLK_GATE_USB2CLK	(14)
+#define SCU0_CLK_GATE_UART4CLK	(15)
+#define SCU0_CLK_GATE_SLICLK	(16)
+#define SCU0_CLK_GATE_DACCLK	(17)
+#define SCU0_CLK_GATE_DP	(18)
+#define SCU0_CLK_GATE_RSV19	(19)
+#define SCU0_CLK_GATE_CRT1CLK	(20)
+#define SCU0_CLK_GATE_CRT2CLK	(21)
+#define SCU0_CLK_GATE_VLCLK	(22)
+#define SCU0_CLK_GATE_ECCCLK	(23)
+#define SCU0_CLK_GATE_RSACLK	(24)
+#define SCU0_CLK_GATE_RVAS0CLK	(25)
+#define SCU0_CLK_GATE_UFSCLK	(26)
+#define SCU0_CLK_GATE_EMMCCLK	(27)
+#define SCU0_CLK_GATE_RVAS1CLK	(28)
+/* reserved 29 ~ 31*/
+#define SOC0_CLK_GATE_NUM	(SCU0_CLK_GATE_RVAS1CLK + 1)
+
+/* SOC0 clk */
+#define SCU0_CLKIN		(SOC0_CLK_GATE_NUM + 0)
+#define SCU0_CLK_24M		(SOC0_CLK_GATE_NUM + 1)
+#define SCU0_CLK_192M		(SOC0_CLK_GATE_NUM + 2)
+#define SCU0_CLK_UART		(SOC0_CLK_GATE_NUM + 3)
+#define SCU0_CLK_PSP		(SOC0_CLK_GATE_NUM + 4)
+#define SCU0_CLK_HPLL		(SOC0_CLK_GATE_NUM + 5)
+#define SCU0_CLK_HPLL_DIV2	(SOC0_CLK_GATE_NUM + 6)
+#define SCU0_CLK_HPLL_DIV4	(SOC0_CLK_GATE_NUM + 7)
+#define SCU0_CLK_DPLL		(SOC0_CLK_GATE_NUM + 8)
+#define SCU0_CLK_MPLL		(SOC0_CLK_GATE_NUM + 9)
+#define SCU0_CLK_MPLL_DIV2	(SOC0_CLK_GATE_NUM + 10)
+#define SCU0_CLK_MPLL_DIV4	(SOC0_CLK_GATE_NUM + 11)
+#define SCU0_CLK_MPLL_DIV8	(SOC0_CLK_GATE_NUM + 12)
+#define SCU0_CLK_D1CLK		(SOC0_CLK_GATE_NUM + 13)
+#define SCU0_CLK_D2CLK		(SOC0_CLK_GATE_NUM + 14)
+#define SCU0_CLK_CRT1		(SOC0_CLK_GATE_NUM + 15)
+#define SCU0_CLK_CRT2		(SOC0_CLK_GATE_NUM + 16)
+#define SCU0_CLK_MPHY		(SOC0_CLK_GATE_NUM + 17)
+#define SCU0_CLK_AXI		(SOC0_CLK_GATE_NUM + 18)
+#define SCU0_CLK_AXI1		(SOC0_CLK_GATE_NUM + 19)
+#define SCU0_CLK_AHB		(SOC0_CLK_GATE_NUM + 20)
+#define SCU0_CLK_APB		(SOC0_CLK_GATE_NUM + 21)
+#define SCU0_CLK_MCLK		(SOC0_CLK_GATE_NUM + 22)
+#define SCU0_CLK_ECLK		(SOC0_CLK_GATE_NUM + 23)
+#define SCU0_CLK_GCLK		(SOC0_CLK_GATE_NUM + 24)
+#define SCU0_CLK_VCLK		(SOC0_CLK_GATE_NUM + 25)
+#define SCU0_CLK_BCLK		(SOC0_CLK_GATE_NUM + 26)
+#define SCU0_CLK_REF		(SOC0_CLK_GATE_NUM + 27)
+#define SCU0_CLK_USB0CLK	(SOC0_CLK_GATE_NUM + 28)
+#define SCU0_CLK_USB1CLK	(SOC0_CLK_GATE_NUM + 29)
+#define SCU0_CLK_USB2CLK	(SOC0_CLK_GATE_NUM + 30)
+#define SCU0_CLK_YCLK		(SOC0_CLK_GATE_NUM + 31)
+#define SCU0_CLK_UART4		(SOC0_CLK_GATE_NUM + 32)
+#define SCU0_CLK_SLI		(SOC0_CLK_GATE_NUM + 33)
+#define SCU0_CLK_ECC		(SOC0_CLK_GATE_NUM + 34)
+#define SCU0_CLK_RSA		(SOC0_CLK_GATE_NUM + 35)
+#define SCU0_CLK_RVAS0		(SOC0_CLK_GATE_NUM + 36)
+#define SCU0_CLK_UFS		(SOC0_CLK_GATE_NUM + 37)
+#define SCU0_CLK_RVAS1		(SOC0_CLK_GATE_NUM + 38)
+#define SCU0_CLK_EMMCMUX	(SOC0_CLK_GATE_NUM + 39)
+#define SCU0_CLK_EMMC		(SOC0_CLK_GATE_NUM + 40)
+#define SCU0_CLK_U2PHY_CLK12M	(SOC0_CLK_GATE_NUM + 41)
+#define SCU0_CLK_U2PHY_REFCLK	(SOC0_CLK_GATE_NUM + 42)
+
+#define SOC0_NUM_CLKS		(SCU0_CLK_U2PHY_REFCLK + 1)
+
+/* SOC1 clk gate */
+#define SCU1_CLK_GATE_LCLK0       (0)
+#define SCU1_CLK_GATE_LCLK1       (1)
+#define SCU1_CLK_GATE_ESPI0CLK    (2)
+#define SCU1_CLK_GATE_ESPI1CLK    (3)
+#define SCU1_CLK_GATE_SDCLK       (4)
+#define SCU1_CLK_GATE_REFCLK      (5)
+#define SCU1_CLK_GATE_RSV5CLK     (6)
+#define SCU1_CLK_GATE_LPCHCLK     (7)
+#define SCU1_CLK_GATE_MAC0CLK     (8)
+#define SCU1_CLK_GATE_MAC1CLK     (9)
+#define SCU1_CLK_GATE_MAC2CLK     (10)
+#define SCU1_CLK_GATE_UART0CLK    (11)
+#define SCU1_CLK_GATE_UART1CLK    (12)
+#define SCU1_CLK_GATE_UART2CLK    (13)
+#define SCU1_CLK_GATE_UART3CLK    (14)
+/* reserved bit 15*/
+#define SCU1_CLK_GATE_I3C0CLK     (16)
+#define SCU1_CLK_GATE_I3C1CLK     (17)
+#define SCU1_CLK_GATE_I3C2CLK     (18)
+#define SCU1_CLK_GATE_I3C3CLK     (19)
+#define SCU1_CLK_GATE_I3C4CLK     (20)
+#define SCU1_CLK_GATE_I3C5CLK     (21)
+#define SCU1_CLK_GATE_I3C6CLK     (22)
+#define SCU1_CLK_GATE_I3C7CLK     (23)
+#define SCU1_CLK_GATE_I3C8CLK     (24)
+#define SCU1_CLK_GATE_I3C9CLK     (25)
+#define SCU1_CLK_GATE_I3C10CLK    (26)
+#define SCU1_CLK_GATE_I3C11CLK    (27)
+#define SCU1_CLK_GATE_I3C12CLK    (28)
+#define SCU1_CLK_GATE_I3C13CLK    (29)
+#define SCU1_CLK_GATE_I3C14CLK    (30)
+#define SCU1_CLK_GATE_I3C15CLK    (31)
+
+#define SCU1_CLK_GATE_UART5CLK    (32 + 0)
+#define SCU1_CLK_GATE_UART6CLK	  (32 + 1)
+#define SCU1_CLK_GATE_UART7CLK    (32 + 2)
+#define SCU1_CLK_GATE_UART8CLK    (32 + 3)
+#define SCU1_CLK_GATE_UART9CLK	  (32 + 4)
+#define SCU1_CLK_GATE_UART10CLK   (32 + 5)
+#define SCU1_CLK_GATE_UART11CLK   (32 + 6)
+#define SCU1_CLK_GATE_UART12CLK   (32 + 7)
+#define SCU1_CLK_GATE_FSICLK      (32 + 8)
+#define SCU1_CLK_GATE_LTPIPHYCLK  (32 + 9)
+#define SCU1_CLK_GATE_LTPICLK     (32 + 10)
+#define SCU1_CLK_GATE_VGALCLK     (32 + 11)
+#define SCU1_CLK_GATE_USBUARTCLK  (32 + 12)
+#define SCU1_CLK_GATE_CANCLK      (32 + 13)
+#define SCU1_CLK_GATE_PCICLK	  (32 + 14)
+#define SCU1_CLK_GATE_SLICLK      (32 + 15)
+
+#define SOC1_CLK_GATE_NUM	(SCU1_CLK_GATE_SLICLK + 1)
+
+/* SOC1 clk */
+#define SCU1_CLKIN		(SOC1_CLK_GATE_NUM + 0)
+#define SCU1_CLK_HPLL		(SOC1_CLK_GATE_NUM + 1)
+#define SCU1_CLK_APLL		(SOC1_CLK_GATE_NUM + 2)
+#define SCU1_CLK_APLL_DIV2	(SOC1_CLK_GATE_NUM + 3)
+#define SCU1_CLK_APLL_DIV4	(SOC1_CLK_GATE_NUM + 4)
+#define SCU1_CLK_DPLL		(SOC1_CLK_GATE_NUM + 5)
+#define SCU1_CLK_UXCLK		(SOC1_CLK_GATE_NUM + 6)
+#define SCU1_CLK_HUXCLK		(SOC1_CLK_GATE_NUM + 7)
+#define SCU1_CLK_UARTX		(SOC1_CLK_GATE_NUM + 8)
+#define SCU1_CLK_HUARTX		(SOC1_CLK_GATE_NUM + 9)
+#define SCU1_CLK_AHB		(SOC1_CLK_GATE_NUM + 10)
+#define SCU1_CLK_APB		(SOC1_CLK_GATE_NUM + 11)
+#define SCU1_CLK_UART0		(SOC1_CLK_GATE_NUM + 12)
+#define SCU1_CLK_UART1		(SOC1_CLK_GATE_NUM + 13)
+#define SCU1_CLK_UART2		(SOC1_CLK_GATE_NUM + 14)
+#define SCU1_CLK_UART3		(SOC1_CLK_GATE_NUM + 15)
+#define SCU1_CLK_UART5		(SOC1_CLK_GATE_NUM + 16)
+#define SCU1_CLK_UART6		(SOC1_CLK_GATE_NUM + 17)
+#define SCU1_CLK_UART7		(SOC1_CLK_GATE_NUM + 18)
+#define SCU1_CLK_UART8		(SOC1_CLK_GATE_NUM + 19)
+#define SCU1_CLK_UART9		(SOC1_CLK_GATE_NUM + 20)
+#define SCU1_CLK_UART10		(SOC1_CLK_GATE_NUM + 21)
+#define SCU1_CLK_UART11		(SOC1_CLK_GATE_NUM + 22)
+#define SCU1_CLK_UART12		(SOC1_CLK_GATE_NUM + 23)
+#define SCU1_CLK_APLL_DIVN	(SOC1_CLK_GATE_NUM + 24)
+#define SCU1_CLK_SDMUX		(SOC1_CLK_GATE_NUM + 25)
+#define SCU1_CLK_SDCLK		(SOC1_CLK_GATE_NUM + 26)
+#define SCU1_CLK_RMII		(SOC1_CLK_GATE_NUM + 27)
+#define SCU1_CLK_RGMII		(SOC1_CLK_GATE_NUM + 28)
+#define SCU1_CLK_MACHCLK	(SOC1_CLK_GATE_NUM + 29)
+#define SCU1_CLK_MAC0RCLK	(SOC1_CLK_GATE_NUM + 30)
+#define SCU1_CLK_MAC1RCLK	(SOC1_CLK_GATE_NUM + 31)
+
+#define SOC1_NUM_CLKS		(SCU1_CLK_MAC1RCLK + 1)
+
+#endif
-- 
2.34.1

[PATCH v1 03/10] clk: ast2700: add clock controller

[Kevin Chen]

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 drivers/clk/Makefile      |    1 +
 drivers/clk/clk-ast2700.c | 1166 +++++++++++++++++++++++++++++++++++++
 2 files changed, 1167 insertions(+)
 create mode 100644 drivers/clk/clk-ast2700.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f793a16cad40..0d5992ea0fa4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI)	+= clk-fsl-sai.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o
 obj-$(CONFIG_COMMON_CLK_ASPEED)		+= clk-aspeed.o
 obj-$(CONFIG_MACH_ASPEED_G6)		+= clk-ast2600.o
+obj-$(CONFIG_MACH_ASPEED_G7)		+= clk-ast2700.o
 obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
 obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_K210)		+= clk-k210.o
diff --git a/drivers/clk/clk-ast2700.c b/drivers/clk/clk-ast2700.c
new file mode 100644
index 000000000000..04049f1f1661
--- /dev/null
+++ b/drivers/clk/clk-ast2700.c
@@ -0,0 +1,1166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright ASPEED Technology
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/aspeed,ast2700-clk.h>
+#include <dt-bindings/reset/aspeed,ast2700-reset.h>
+
+#define SCU_CLK_24MHZ 24000000
+#define SCU_CLK_25MHZ 25000000
+#define SCU_CLK_192MHZ 192000000
+/* SOC0 USB2 PHY CLK*/
+#define SCU_CLK_12MHZ 12000000
+/* SOC0 */
+#define SCU0_HWSTRAP1 0x010
+#define SCU0_CLK_STOP 0x240
+#define SCU0_CLK_SEL1 0x280
+#define SCU0_CLK_SEL2 0x284
+#define GET_USB_REFCLK_DIV(x) ((GENMASK(23, 20) & (x)) >> 20)
+#define UART_DIV13_EN BIT(30)
+#define SCU0_HPLL_PARAM 0x300
+#define SCU0_DPLL_PARAM 0x308
+#define SCU0_MPLL_PARAM 0x310
+#define SCU0_D1CLK_PARAM 0x320
+#define SCU0_D2CLK_PARAM 0x330
+#define SCU0_CRT1CLK_PARAM 0x340
+#define SCU0_CRT2CLK_PARAM 0x350
+#define SCU0_MPHYCLK_PARAM 0x360
+
+/* SOC1 */
+#define SCU1_CLK_STOP 0x240
+#define SCU1_CLK_STOP2 0x260
+#define SCU1_CLK_SEL1 0x280
+#define SCU1_CLK_SEL2 0x284
+#define UXCLK_MASK GENMASK(1, 0)
+#define HUXCLK_MASK GENMASK(4, 3)
+#define SCU1_HPLL_PARAM 0x300
+#define SCU1_APLL_PARAM 0x310
+#define SCU1_DPLL_PARAM 0x320
+#define SCU1_UXCLK_CTRL 0x330
+#define SCU1_HUXCLK_CTRL 0x334
+#define SCU1_MAC12_CLK_DLY 0x390
+#define SCU1_MAC12_CLK_DLY_100M 0x394
+#define SCU1_MAC12_CLK_DLY_10M 0x398
+
+/*
+ * MAC Clock Delay settings
+ */
+#define MAC_CLK_RMII1_50M_RCLK_O_CTRL		BIT(30)
+#define   MAC_CLK_RMII1_50M_RCLK_O_DIS		0
+#define   MAC_CLK_RMII1_50M_RCLK_O_EN		1
+#define MAC_CLK_RMII0_50M_RCLK_O_CTRL		BIT(29)
+#define   MAC_CLK_RMII0_5M_RCLK_O_DIS		0
+#define   MAC_CLK_RMII0_5M_RCLK_O_EN		1
+#define MAC_CLK_RMII_TXD_FALLING_2		BIT(27)
+#define MAC_CLK_RMII_TXD_FALLING_1		BIT(26)
+#define MAC_CLK_RXCLK_INV_2			BIT(25)
+#define MAC_CLK_RXCLK_INV_1			BIT(24)
+#define MAC_CLK_1G_INPUT_DELAY_2		GENMASK(23, 18)
+#define MAC_CLK_1G_INPUT_DELAY_1		GENMASK(17, 12)
+#define MAC_CLK_1G_OUTPUT_DELAY_2		GENMASK(11, 6)
+#define MAC_CLK_1G_OUTPUT_DELAY_1		GENMASK(5, 0)
+
+#define MAC_CLK_100M_10M_RESERVED		GENMASK(31, 26)
+#define MAC_CLK_100M_10M_RXCLK_INV_2		BIT(25)
+#define MAC_CLK_100M_10M_RXCLK_INV_1		BIT(24)
+#define MAC_CLK_100M_10M_INPUT_DELAY_2		GENMASK(23, 18)
+#define MAC_CLK_100M_10M_INPUT_DELAY_1		GENMASK(17, 12)
+#define MAC_CLK_100M_10M_OUTPUT_DELAY_2		GENMASK(11, 6)
+#define MAC_CLK_100M_10M_OUTPUT_DELAY_1		GENMASK(5, 0)
+
+#define AST2700_DEF_MAC12_DELAY_1G	0x00CF4D75
+#define AST2700_DEF_MAC12_DELAY_100M	0x00410410
+#define AST2700_DEF_MAC12_DELAY_10M	0x00410410
+
+struct mac_delay_config {
+	u32 tx_delay_1000;
+	u32 rx_delay_1000;
+	u32 tx_delay_100;
+	u32 rx_delay_100;
+	u32 tx_delay_10;
+	u32 rx_delay_10;
+};
+
+/* Globally visible clocks */
+static DEFINE_SPINLOCK(ast2700_clk_lock);
+
+/* Division of RGMII Clock */
+static const struct clk_div_table ast2700_rgmii_div_table[] = {
+	{ 0x0, 4 },
+	{ 0x1, 4 },
+	{ 0x2, 6 },
+	{ 0x3, 8 },
+	{ 0x4, 10 },
+	{ 0x5, 12 },
+	{ 0x6, 14 },
+	{ 0x7, 16 },
+	{ 0 }
+};
+
+/* Division of RMII Clock */
+static const struct clk_div_table ast2700_rmii_div_table[] = {
+	{ 0x0, 8 },
+	{ 0x1, 8 },
+	{ 0x2, 12 },
+	{ 0x3, 16 },
+	{ 0x4, 20 },
+	{ 0x5, 24 },
+	{ 0x6, 28 },
+	{ 0x7, 32 },
+	{ 0 }
+};
+
+/* Division of HCLK/SDIO/MAC/apll_divn CLK */
+static const struct clk_div_table ast2700_clk_div_table[] = {
+	{ 0x0, 2 },
+	{ 0x1, 2 },
+	{ 0x2, 3 },
+	{ 0x3, 4 },
+	{ 0x4, 5 },
+	{ 0x5, 6 },
+	{ 0x6, 7 },
+	{ 0x7, 8 },
+	{ 0 }
+};
+
+/* Division of PCLK/EMMC CLK */
+static const struct clk_div_table ast2700_clk_div_table2[] = {
+	{ 0x0, 2 },
+	{ 0x1, 4 },
+	{ 0x2, 6 },
+	{ 0x3, 8 },
+	{ 0x4, 10 },
+	{ 0x5, 12 },
+	{ 0x6, 14 },
+	{ 0x7, 16 },
+	{ 0 }
+};
+
+/* HPLL/DPLL: 2000Mhz(default) */
+struct clk_hw *ast2700_soc0_hw_pll(const char *name, const char *parent_name, u32 val)
+{
+	unsigned int mult, div;
+
+	if (val & BIT(24)) {
+		/* Pass through mode */
+		mult = 1;
+		div = 1;
+	} else {
+		/* F = CLKIN(25MHz) * [(M+1) / 2(N+1)] / (P+1) */
+		u32 m = val & 0x1fff;
+		u32 n = (val >> 13) & 0x3f;
+		u32 p = (val >> 19) & 0xf;
+
+		mult = (m + 1) / (2 * (n + 1));
+		div = (p + 1);
+	}
+
+	return clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+};
+
+/* MPLL 1600Mhz(default) */
+struct clk_hw *ast2700_calc_mpll(const char *name, const char *parent_name, u32 val)
+{
+	unsigned int mult, div;
+
+	if (val & BIT(24)) {
+		/* Pass through mode */
+		div = 1;
+		mult = div;
+	} else {
+		/* F = CLKIN(25MHz) * [CLKF/(CLKR+1)] /(CLKOD+1) */
+		u32 m = val & 0x1fff;
+		u32 n = (val >> 13) & 0x3f;
+		u32 p = (val >> 19) & 0xf;
+
+		mult = m / (n + 1);
+		div = (p + 1);
+	}
+	return clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+};
+
+static struct clk_hw *ast2700_calc_uclk(const char *name, u32 val)
+{
+	unsigned int mult, div;
+
+	/* UARTCLK = UXCLK * R / (N * 2) */
+	u32 r = val & 0xff;
+	u32 n = (val >> 8) & 0x3ff;
+
+	mult = r;
+	div = n * 2;
+
+	return clk_hw_register_fixed_factor(NULL, name, "uxclk", 0, mult, div);
+};
+
+static struct clk_hw *ast2700_calc_huclk(const char *name, u32 val)
+{
+	unsigned int mult, div;
+
+	/* UARTCLK = UXCLK * R / (N * 2) */
+	u32 r = val & 0xff;
+	u32 n = (val >> 8) & 0x3ff;
+
+	mult = r;
+	div = n * 2;
+
+	return clk_hw_register_fixed_factor(NULL, name, "huxclk", 0, mult, div);
+};
+
+struct clk_hw *ast2700_calc_soc1_pll(const char *name, const char *parent_name, u32 val)
+{
+	unsigned int mult, div;
+
+	if (val & BIT(24)) {
+		/* Pass through mode */
+		div = 1;
+		mult = div;
+	} else {
+		/* F = 25Mhz * [(M + 1) / (n + 1)] / (p + 1) */
+		u32 m = val & 0x1fff;
+		u32 n = (val >> 13) & 0x3f;
+		u32 p = (val >> 19) & 0xf;
+
+		mult = (m + 1) / (n + 1);
+		div = (p + 1);
+	}
+	return clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+};
+
+static int ast2700_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	u32 clk = BIT(gate->bit_idx);
+	u32 reg;
+
+	reg = readl(gate->reg);
+
+	return !(reg & clk);
+}
+
+static int ast2700_clk_enable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	u32 clk = BIT(gate->bit_idx);
+
+	if (readl(gate->reg) & clk)
+		writel(clk, gate->reg + 0x04);
+
+	return 0;
+}
+
+static void ast2700_clk_disable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	u32 clk = BIT(gate->bit_idx);
+
+	/* Clock is set to enable, so use write to set register */
+	writel(clk, gate->reg);
+}
+
+static const struct clk_ops ast2700_clk_gate_ops = {
+	.enable = ast2700_clk_enable,
+	.disable = ast2700_clk_disable,
+	.is_enabled = ast2700_clk_is_enabled,
+};
+
+static struct clk_hw *ast2700_clk_hw_register_gate(struct device *dev, const char *name,
+						   const char *parent_name, unsigned long flags,
+						   void __iomem *reg, u8 clock_idx,
+						   u8 clk_gate_flags, spinlock_t *lock)
+{
+	struct clk_gate *gate;
+	struct clk_hw *hw;
+	struct clk_init_data init;
+	int ret = -EINVAL;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &ast2700_clk_gate_ops;
+	init.flags = flags;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.num_parents = parent_name ? 1 : 0;
+
+	gate->reg = reg;
+	gate->bit_idx = clock_idx;
+	gate->flags = clk_gate_flags;
+	gate->lock = lock;
+	gate->hw.init = &init;
+
+	hw = &gate->hw;
+	ret = clk_hw_register(dev, hw);
+	if (ret) {
+		kfree(gate);
+		hw = ERR_PTR(ret);
+	}
+
+	return hw;
+}
+
+struct ast2700_reset {
+	void __iomem *base;
+	struct reset_controller_dev rcdev;
+};
+
+#define to_rc_data(p) container_of(p, struct ast2700_reset, rcdev)
+
+static int ast2700_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct ast2700_reset *rc = to_rc_data(rcdev);
+	u32 rst = BIT(id % 32);
+	u32 reg = id >= 32 ? 0x220 : 0x200;
+
+	writel(rst, rc->base + reg);
+	return 0;
+}
+
+static int ast2700_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct ast2700_reset *rc = to_rc_data(rcdev);
+	u32 rst = BIT(id % 32);
+	u32 reg = id >= 32 ? 0x220 : 0x200;
+
+	/* Use set to clear register */
+	writel(rst, rc->base + reg + 0x04);
+	return 0;
+}
+
+static int ast2700_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct ast2700_reset *rc = to_rc_data(rcdev);
+	u32 rst = BIT(id % 32);
+	u32 reg = id >= 32 ? 0x220 : 0x200;
+
+	return (readl(rc->base + reg) & rst);
+}
+
+static const struct reset_control_ops ast2700_reset_ops = {
+	.assert = ast2700_reset_assert,
+	.deassert = ast2700_reset_deassert,
+	.status = ast2700_reset_status,
+};
+
+static const char *const sdclk_sel[] = {
+	"soc1-hpll",
+	"soc1-apll",
+};
+
+static const char *const uartclk_sel[] = {
+	"uartxclk",
+	"huartxclk",
+};
+
+static const char *const uxclk_sel[] = {
+	"soc1-apll_div4",
+	"soc1-apll_div2",
+	"soc1-apll",
+	"soc1-hpll",
+};
+
+static void ast2700_soc1_configure_mac01_clk(struct device_node *np)
+{
+	void __iomem *clk_base;
+	struct mac_delay_config mac_cfg;
+	u32 reg[3];
+	int ret;
+
+	clk_base = of_iomap(np, 0);
+	WARN_ON(!clk_base);
+
+	reg[0] = AST2700_DEF_MAC12_DELAY_1G;
+	reg[1] = AST2700_DEF_MAC12_DELAY_100M;
+	reg[2] = AST2700_DEF_MAC12_DELAY_10M;
+
+	ret = of_property_read_u32_array(np, "mac0-clk-delay", (u32 *)&mac_cfg,
+					 sizeof(mac_cfg) / sizeof(u32));
+	if (!ret) {
+		reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_1);
+		reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, mac_cfg.rx_delay_1000) |
+			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, mac_cfg.tx_delay_1000);
+
+		reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1);
+		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac_cfg.rx_delay_100) |
+			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac_cfg.tx_delay_100);
+
+		reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1);
+		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac_cfg.rx_delay_10) |
+			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac_cfg.tx_delay_10);
+	}
+
+	ret = of_property_read_u32_array(np, "mac1-clk-delay", (u32 *)&mac_cfg,
+					 sizeof(mac_cfg) / sizeof(u32));
+	if (!ret) {
+		reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_2 | MAC_CLK_1G_OUTPUT_DELAY_2);
+		reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, mac_cfg.rx_delay_1000) |
+			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, mac_cfg.tx_delay_1000);
+
+		reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
+		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac_cfg.rx_delay_100) |
+			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac_cfg.tx_delay_100);
+
+		reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
+		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac_cfg.rx_delay_10) |
+			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac_cfg.tx_delay_10);
+	}
+
+	reg[0] |= (readl(clk_base + SCU1_MAC12_CLK_DLY) & ~GENMASK(25, 0));
+	writel(reg[0], clk_base + SCU1_MAC12_CLK_DLY);
+	writel(reg[1], clk_base + SCU1_MAC12_CLK_DLY_100M);
+	writel(reg[2], clk_base + SCU1_MAC12_CLK_DLY_10M);
+}
+
+static int ast2700_soc1_clk_init(struct device_node *soc1_node)
+{
+	struct clk_hw_onecell_data *clk_data;
+	struct ast2700_reset *reset;
+	u32 uart_clk_source = 0;
+	void __iomem *clk_base;
+	struct clk_hw **clks;
+	u32 val, id;
+	int ret;
+
+	clk_base = of_iomap(soc1_node, 0);
+	WARN_ON(!clk_base);
+
+	clk_data = kzalloc(struct_size(clk_data, hws, SOC1_NUM_CLKS), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->num = SOC1_NUM_CLKS;
+	clks = clk_data->hws;
+
+	reset = kzalloc(sizeof(*reset), GFP_KERNEL);
+	if (!reset)
+		return -ENOMEM;
+
+	reset->base = clk_base;
+
+	reset->rcdev.owner = THIS_MODULE;
+	reset->rcdev.nr_resets = SOC1_RESET_NUMS;
+	reset->rcdev.ops = &ast2700_reset_ops;
+	reset->rcdev.of_node = soc1_node;
+
+	ret = reset_controller_register(&reset->rcdev);
+	if (ret) {
+		pr_err("soc1 failed to register reset controller\n");
+		return ret;
+	}
+	/*
+	 * Ast2700 A0 workaround:
+	 * I3C reset should assert all of the I3C controllers simultaneously.
+	 * Otherwise, it may lead to failure in accessing I3C registers.
+	 */
+	for (id = SCU1_RESET_I3C0; id <= SCU1_RESET_I3C15; id++)
+		ast2700_reset_assert(&reset->rcdev, id);
+
+	clks[SCU1_CLKIN] =
+		clk_hw_register_fixed_rate(NULL, "soc1-clkin", NULL, 0, SCU_CLK_25MHZ);
+
+	/* HPLL 1000Mhz */
+	val = readl(clk_base + SCU1_HPLL_PARAM);
+	clks[SCU1_CLK_HPLL] = ast2700_calc_soc1_pll("soc1-hpll", "soc1-clkin", val);
+
+	/* HPLL 800Mhz */
+	val = readl(clk_base + SCU1_APLL_PARAM);
+	clks[SCU1_CLK_APLL] = ast2700_calc_soc1_pll("soc1-apll", "soc1-clkin", val);
+
+	clks[SCU1_CLK_APLL_DIV2] =
+		clk_hw_register_fixed_factor(NULL, "soc1-apll_div2", "soc1-apll", 0, 1, 2);
+
+	clks[SCU1_CLK_APLL_DIV4] =
+		clk_hw_register_fixed_factor(NULL, "soc1-apll_div4", "soc1-apll", 0, 1, 4);
+
+	val = readl(clk_base + SCU1_DPLL_PARAM);
+	clks[SCU1_CLK_DPLL] = ast2700_calc_soc1_pll("dpll", "soc1-clkin", val);
+
+	/* uxclk mux selection */
+	clks[SCU1_CLK_UXCLK] =
+		clk_hw_register_mux(NULL, "uxclk", uxclk_sel, ARRAY_SIZE(uxclk_sel),
+				    0, clk_base + SCU1_CLK_SEL2,
+				    0, 2, 0, &ast2700_clk_lock);
+
+	val = readl(clk_base + SCU1_UXCLK_CTRL);
+	clks[SCU1_CLK_UARTX] = ast2700_calc_uclk("uartxclk", val);
+
+	/* huxclk mux selection */
+	clks[SCU1_CLK_HUXCLK] =
+		clk_hw_register_mux(NULL, "huxclk", uxclk_sel, ARRAY_SIZE(uxclk_sel),
+				    0, clk_base + SCU1_CLK_SEL2,
+				    3, 2, 0, &ast2700_clk_lock);
+
+	val = readl(clk_base + SCU1_HUXCLK_CTRL);
+	clks[SCU1_CLK_HUARTX] = ast2700_calc_huclk("huartxclk", val);
+
+	/* AHB CLK = 200Mhz */
+	clks[SCU1_CLK_AHB] =
+		clk_hw_register_divider_table(NULL, "soc1-ahb", "soc1-hpll",
+					      0, clk_base + SCU1_CLK_SEL2,
+					      20, 3, 0, ast2700_clk_div_table, &ast2700_clk_lock);
+
+	/* APB CLK = 100Mhz */
+	clks[SCU1_CLK_APB] =
+		clk_hw_register_divider_table(NULL, "soc1-apb", "soc1-hpll",
+					      0, clk_base + SCU1_CLK_SEL1,
+					      18, 3, 0, ast2700_clk_div_table2, &ast2700_clk_lock);
+
+	/* RMII */
+	clks[SCU1_CLK_RMII] =
+		clk_hw_register_divider_table(NULL, "rmii", "soc1-hpll",
+					      0, clk_base + SCU1_CLK_SEL1,
+					      21, 3, 0, ast2700_rmii_div_table, &ast2700_clk_lock);
+
+	/* RMII0 50MHz (RCLK) output enable */
+	clks[SCU1_CLK_MAC0RCLK] =
+		clk_hw_register_gate(NULL, "mac0rclk", "rmii", 0,
+				     clk_base + SCU1_MAC12_CLK_DLY, 29,
+				     0, &ast2700_clk_lock);
+
+	/* RMII1 50MHz (RCLK) output enable */
+	clks[SCU1_CLK_MAC1RCLK] =
+		clk_hw_register_gate(NULL, "mac1rclk", "rmii", 0,
+				     clk_base + SCU1_MAC12_CLK_DLY, 30,
+				     0, &ast2700_clk_lock);
+
+	/* RGMII */
+	clks[SCU1_CLK_RGMII] =
+		clk_hw_register_divider_table(NULL, "rgmii", "soc1-hpll",
+					      0, clk_base + SCU1_CLK_SEL1,
+					      25, 3, 0, ast2700_rgmii_div_table, &ast2700_clk_lock);
+
+	/* MAC HCLK */
+	clks[SCU1_CLK_MACHCLK] =
+		clk_hw_register_divider_table(NULL, "machclk", "soc1-hpll",
+					      0, clk_base + SCU1_CLK_SEL1,
+					      29, 3, 0, ast2700_clk_div_table, &ast2700_clk_lock);
+
+	/* MAC0/1 RGMII/RMII Clock Delay */
+	ast2700_soc1_configure_mac01_clk(soc1_node);
+
+	clks[SCU1_CLK_GATE_LCLK0] =
+		ast2700_clk_hw_register_gate(NULL, "lclk0-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     0, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_LCLK0] =
+		ast2700_clk_hw_register_gate(NULL, "lclk1-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_ESPI0CLK] =
+		ast2700_clk_hw_register_gate(NULL, "espi0clk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     2, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_ESPI1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "espi1clk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     3, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_APLL_DIVN] =
+		clk_hw_register_divider_table(NULL, "soc1-apll_divn", "soc1-apll",
+					      0, clk_base + SCU1_CLK_SEL2,
+					      8, 3, 0, ast2700_clk_div_table, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_SDMUX] =
+		clk_hw_register_mux(NULL, "sdclk-mux", sdclk_sel, ARRAY_SIZE(sdclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    13, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_SDCLK] =
+		clk_hw_register_divider_table(NULL, "sdclk", "sdclk-mux",
+					      0, clk_base + SCU1_CLK_SEL1,
+					      14, 3, 0, ast2700_clk_div_table, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_SDCLK] =
+		ast2700_clk_hw_register_gate(NULL, "sdclk-gate", "sdclk",
+					     0, clk_base + SCU1_CLK_STOP,
+					     4, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_REFCLK] =
+		ast2700_clk_hw_register_gate(NULL, "soc1-refclk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     6, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_LPCHCLK] =
+		ast2700_clk_hw_register_gate(NULL, "lpchclk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     7, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_MAC0CLK] =
+		ast2700_clk_hw_register_gate(NULL, "mac0clk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP,
+					     8, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_MAC1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "mac1clk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP,
+					     9, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_MAC2CLK] =
+		ast2700_clk_hw_register_gate(NULL, "mac2clk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP,
+					     10, 0, &ast2700_clk_lock);
+
+	of_property_read_u32(soc1_node, "uart-clk-source", &uart_clk_source);
+	if (uart_clk_source) {
+		val = readl(clk_base + SCU1_CLK_SEL1) & ~GENMASK(12, 0);
+		uart_clk_source &= GENMASK(12, 0);
+		writel(val | uart_clk_source, clk_base + SCU1_CLK_SEL1);
+	}
+
+	//UART0
+	clks[SCU1_CLK_UART0] =
+		clk_hw_register_mux(NULL, "uart0clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    0, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART0CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart0clk-gate", "uart0clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     11, 0, &ast2700_clk_lock);
+
+	//UART1
+	clks[SCU1_CLK_UART1] =
+		clk_hw_register_mux(NULL, "uart1clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    1, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart1clk-gate", "uart1clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     12, 0, &ast2700_clk_lock);
+
+	//UART2
+	clks[SCU1_CLK_UART2] =
+		clk_hw_register_mux(NULL, "uart2clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    2, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART2CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart2clk-gate", "uart2clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     13, 0, &ast2700_clk_lock);
+
+	//UART3
+	clks[SCU1_CLK_UART3] =
+		clk_hw_register_mux(NULL, "uart3clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    3, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART3CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart3clk-gate", "uart3clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP,
+					     14, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C0CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c0clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     16, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c1clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     17, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C2CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c2clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     18, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C3CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c3clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     19, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C4CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c4clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     20, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C5CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c5clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     21, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C6CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c6clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     22, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C7CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c7clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     23, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C8CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c8clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     24, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C9CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c9clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     25, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C10CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c10clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     26, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C11CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c11clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     27, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C12CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c12clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     28, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C13CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c13clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     29, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C14CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c14clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     30, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_I3C15CLK] =
+		ast2700_clk_hw_register_gate(NULL, "i3c15clk-gate", "soc1-ahb",
+					     0, clk_base + SCU1_CLK_STOP,
+					     31, 0, &ast2700_clk_lock);
+
+	/*clk stop 2 */
+	//UART5
+	clks[SCU1_CLK_UART5] =
+		clk_hw_register_mux(NULL, "uart5clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    5, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART5CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart5clk-gate", "uart5clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     0, 0, &ast2700_clk_lock);
+
+	//UART6
+	clks[SCU1_CLK_UART6] =
+		clk_hw_register_mux(NULL, "uart6clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    6, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART6CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart6clk-gate", "uart6clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     1, 0, &ast2700_clk_lock);
+
+	//UART7
+	clks[SCU1_CLK_UART7] =
+		clk_hw_register_mux(NULL, "uart7clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    7, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART7CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart7clk-gate", "uart7clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     2, 0, &ast2700_clk_lock);
+
+	//UART8
+	clks[SCU1_CLK_UART8] =
+		clk_hw_register_mux(NULL, "uart8clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    8, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART8CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart8clk-gate", "uart8clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     3, 0, &ast2700_clk_lock);
+
+	//UART9
+	clks[SCU1_CLK_UART9] =
+		clk_hw_register_mux(NULL, "uart9clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    9, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART9CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart9clk-gate", "uart9clk",
+					     0, clk_base + SCU1_CLK_STOP2,
+					     4, 0, &ast2700_clk_lock);
+
+	//UART10
+	clks[SCU1_CLK_UART10] =
+		clk_hw_register_mux(NULL, "uart10clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    10, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART10CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart10clk-gate", "uart10clk",
+					     0, clk_base + SCU1_CLK_STOP2,
+					     5, 0, &ast2700_clk_lock);
+
+	//UART11
+	clks[SCU1_CLK_UART11] =
+		clk_hw_register_mux(NULL, "uart11clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    11, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART11CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart11clk-gate", "uart11clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     6, 0, &ast2700_clk_lock);
+
+	//uart12: call bmc uart
+	clks[SCU1_CLK_UART12] =
+		clk_hw_register_mux(NULL, "uart12clk", uartclk_sel, ARRAY_SIZE(uartclk_sel),
+				    0, clk_base + SCU1_CLK_SEL1,
+				    12, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_UART12CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart12clk-gate", "uart12clk",
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     7, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_FSICLK] =
+		ast2700_clk_hw_register_gate(NULL, "fsiclk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP2,
+					     8, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_LTPIPHYCLK] =
+		ast2700_clk_hw_register_gate(NULL, "ltpiphyclk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP2,
+					     9, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_LTPICLK] =
+		ast2700_clk_hw_register_gate(NULL, "ltpiclk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP2,
+					     10, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_VGALCLK] =
+		ast2700_clk_hw_register_gate(NULL, "vgalclk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     11, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_USBUARTCLK] =
+		ast2700_clk_hw_register_gate(NULL, "usbuartclk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP2,
+					     12, 0, &ast2700_clk_lock);
+
+	clk_hw_register_fixed_factor(NULL, "canclk", "soc1-apll", 0, 1, 10);
+
+	clks[SCU1_CLK_GATE_CANCLK] =
+		ast2700_clk_hw_register_gate(NULL, "canclk-gate", "canclk",
+					     0, clk_base + SCU1_CLK_STOP2,
+					     13, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_PCICLK] =
+		ast2700_clk_hw_register_gate(NULL, "pciclk-gate", NULL,
+					     0, clk_base + SCU1_CLK_STOP2,
+					     14, 0, &ast2700_clk_lock);
+
+	clks[SCU1_CLK_GATE_SLICLK] =
+		ast2700_clk_hw_register_gate(NULL, "sliclk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU1_CLK_STOP2,
+					     15, 0, &ast2700_clk_lock);
+
+	of_clk_add_hw_provider(soc1_node, of_clk_hw_onecell_get, clk_data);
+
+	return 0;
+};
+
+static const char *const pspclk_sel[] = {
+	"soc0-mpll",
+	"soc0-hpll",
+};
+
+static const char *const soc0_uartclk_sel[] = {
+	"soc0-clk24Mhz",
+	"soc0-clk192Mhz",
+};
+
+static const char *const emmcclk_sel[] = {
+	"soc0-mpll_div4",
+	"soc0-hpll_div4",
+};
+
+static int ast2700_soc0_clk_init(struct device_node *soc0_node)
+{
+	struct clk_hw_onecell_data *clk_data;
+	void __iomem *clk_base;
+	struct ast2700_reset *reset;
+	struct clk_hw **clks;
+	int div;
+	u32 val;
+	int ret;
+
+	clk_data = kzalloc(struct_size(clk_data, hws, SOC0_NUM_CLKS), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->num = SOC0_NUM_CLKS;
+	clks = clk_data->hws;
+
+	clk_base = of_iomap(soc0_node, 0);
+	if (WARN_ON(IS_ERR(clk_base)))
+		return PTR_ERR(clk_base);
+
+	reset = kzalloc(sizeof(*reset), GFP_KERNEL);
+	if (!reset)
+		return -ENOMEM;
+
+	reset->base = clk_base;
+
+	reset->rcdev.owner = THIS_MODULE;
+	reset->rcdev.nr_resets = SOC0_RESET_NUMS;
+	reset->rcdev.ops = &ast2700_reset_ops;
+	reset->rcdev.of_node = soc0_node;
+
+	ret = reset_controller_register(&reset->rcdev);
+	if (ret) {
+		pr_err("soc0 failed to register reset controller\n");
+		return ret;
+	}
+
+	//refclk
+	clks[SCU0_CLKIN] =
+		clk_hw_register_fixed_rate(NULL, "soc0-clkin", NULL, 0, SCU_CLK_25MHZ);
+
+	clks[SCU0_CLK_24M] =
+		clk_hw_register_fixed_rate(NULL, "soc0-clk24Mhz", NULL, 0, SCU_CLK_24MHZ);
+
+	clks[SCU0_CLK_192M] =
+		clk_hw_register_fixed_rate(NULL, "soc0-clk192Mhz", NULL, 0, SCU_CLK_192MHZ);
+
+	//hpll
+	val = readl(clk_base + SCU0_HWSTRAP1);
+	if ((val & GENMASK(3, 2)) != 0) {
+		switch ((val & GENMASK(3, 2)) >> 2) {
+		case 1:
+			clks[SCU0_CLK_HPLL] =
+				clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1900000000);
+			break;
+		case 2:
+			clks[SCU0_CLK_HPLL] =
+				clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1800000000);
+			break;
+		case 3:
+			clks[SCU0_CLK_HPLL] =
+				clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1700000000);
+			break;
+		}
+	} else {
+		val = readl(clk_base + SCU0_HPLL_PARAM);
+		clks[SCU0_CLK_HPLL] = ast2700_soc0_hw_pll("soc0-hpll", "soc0-clkin", val);
+	}
+	clks[SCU0_CLK_HPLL_DIV2] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div2", "soc0-hpll", 0, 1, 2);
+	clks[SCU0_CLK_HPLL_DIV4] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div4", "soc0-hpll", 0, 1, 4);
+
+	//dpll
+	val = readl(clk_base + SCU0_DPLL_PARAM);
+	clks[SCU0_CLK_DPLL] = ast2700_soc0_hw_pll("dpll", "soc0-clkin", val);
+
+	//mpll
+	val = readl(clk_base + SCU0_MPLL_PARAM);
+	clks[SCU0_CLK_MPLL] = ast2700_calc_mpll("soc0-mpll", "soc0-clkin", val);
+	clks[SCU0_CLK_MPLL_DIV2] = clk_hw_register_fixed_factor(NULL, "soc0-mpll_div2", "soc0-mpll", 0, 1, 2);
+	clks[SCU0_CLK_MPLL_DIV4] = clk_hw_register_fixed_factor(NULL, "soc0-mpll_div4", "soc0-mpll", 0, 1, 4);
+	clks[SCU0_CLK_MPLL_DIV8] = clk_hw_register_fixed_factor(NULL, "soc0-mpll_div8", "soc0-mpll", 0, 1, 8);
+
+	val = readl(clk_base + SCU0_D1CLK_PARAM);
+	clks[SCU0_CLK_D1CLK] = ast2700_soc0_hw_pll("d1clk", "soc0-clkin", val);
+
+	val = readl(clk_base + SCU0_D2CLK_PARAM);
+	clks[SCU0_CLK_D2CLK] = ast2700_soc0_hw_pll("d2clk", "soc0-clkin", val);
+
+	val = readl(clk_base + SCU0_CRT1CLK_PARAM);
+	clks[SCU0_CLK_CRT1] = ast2700_soc0_hw_pll("crt1clk", "soc0-clkin", val);
+
+	val = readl(clk_base + SCU0_CRT2CLK_PARAM);
+	clks[SCU0_CLK_CRT2] = ast2700_soc0_hw_pll("crt2clk", "soc0-clkin", val);
+
+	val = readl(clk_base + SCU0_MPHYCLK_PARAM);
+	clks[SCU0_CLK_MPHY] = clk_hw_register_fixed_factor(NULL, "mphyclk", "soc0-hpll", 0, 1, val + 1);
+
+	clks[SCU0_CLK_PSP] =
+		clk_hw_register_mux(NULL, "pspclk", pspclk_sel, ARRAY_SIZE(pspclk_sel),
+				    0, clk_base + SCU0_HWSTRAP1,
+				    4, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_AXI] =
+		clk_hw_register_fixed_factor(NULL, "axi0clk", "pspclk", 0, 1, 2);
+
+	val = readl(clk_base + SCU0_HWSTRAP1);
+	if (val & BIT(7)) {
+		clks[SCU0_CLK_AHB] =
+			clk_hw_register_divider_table(NULL, "soc0-ahb", "soc0-hpll",
+						      0, clk_base + SCU0_HWSTRAP1,
+						      5, 2, 0, ast2700_clk_div_table, &ast2700_clk_lock);
+	} else {
+		clks[SCU0_CLK_AHB] =
+			clk_hw_register_divider_table(NULL, "soc0-ahb", "soc0-mpll",
+						      0, clk_base + SCU0_HWSTRAP1,
+						      5, 2, 0, ast2700_clk_div_table, &ast2700_clk_lock);
+	}
+
+	clks[SCU0_CLK_AXI1] =
+		clk_hw_register_fixed_factor(NULL, "axi1clk", "soc0-ahb", 0, 1, 2);
+
+	clks[SCU0_CLK_APB] =
+		clk_hw_register_divider_table(NULL, "soc0-apb", "axi0clk",
+					      0, clk_base + SCU0_CLK_SEL1,
+					      23, 3, 0, ast2700_clk_div_table2, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_MCLK] =
+		ast2700_clk_hw_register_gate(NULL, "mclk", "soc0-mpll",
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     0, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_ECLK] =
+		ast2700_clk_hw_register_gate(NULL, "eclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     1, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_GCLK] =
+		ast2700_clk_hw_register_gate(NULL, "gclk", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     2, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_VCLK] =
+		ast2700_clk_hw_register_gate(NULL, "vclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     3, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_BCLK] =
+		ast2700_clk_hw_register_gate(NULL, "bclk", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     4, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_D1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "d1clk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     5, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_REFCLK] =
+		ast2700_clk_hw_register_gate(NULL, "soc0-refclk-gate", "soc0-clkin",
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     6, 0, &ast2700_clk_lock);
+
+	div = (GET_USB_REFCLK_DIV(readl(clk_base + SCU0_CLK_SEL2)) + 1) * 2;
+	clks[SCU0_CLK_U2PHY_REFCLK] = clk_hw_register_fixed_factor(NULL, "xhci_ref_clk", "soc0-mpll_div8", 0, 1, div);
+
+	clks[SCU0_CLK_U2PHY_CLK12M] =
+		clk_hw_register_fixed_rate(NULL, "xhci_suspend_clk", NULL, 0, SCU_CLK_12MHZ);
+
+	clks[SCU0_CLK_GATE_USB0CLK] =
+		ast2700_clk_hw_register_gate(NULL, "usb0clk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     7, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_USB1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "usb1clk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     9, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_D2CLK] =
+		ast2700_clk_hw_register_gate(NULL, "d2clk-gate", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     10, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_YCLK] =
+		ast2700_clk_hw_register_gate(NULL, "yclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     13, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_USB2CLK] =
+		ast2700_clk_hw_register_gate(NULL, "usb2clk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     14, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_UART] =
+		clk_hw_register_mux(NULL, "soc0-uartclk", soc0_uartclk_sel, ARRAY_SIZE(soc0_uartclk_sel),
+				    0, clk_base + SCU0_CLK_SEL2,
+				    14, 1, 0, &ast2700_clk_lock);
+
+	if (readl(clk_base + SCU0_CLK_SEL2) & UART_DIV13_EN)
+		div = 13;
+	else
+		div = 1;
+
+	clks[SCU0_CLK_UART4] =
+		clk_hw_register_fixed_factor(NULL, "uart4clk", "soc0-uartclk", 0, 1, div);
+
+	clks[SCU0_CLK_GATE_UART4CLK] =
+		ast2700_clk_hw_register_gate(NULL, "uart4clk-gate", "uart4clk",
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     15, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_DACCLK] =
+		ast2700_clk_hw_register_gate(NULL, "dacclk", NULL,
+					     CLK_IS_CRITICAL, clk_base + SCU0_CLK_STOP,
+					     17, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_CRT1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "crt1clk-gate", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     20, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_CRT2CLK] =
+		ast2700_clk_hw_register_gate(NULL, "crt2clk-gate", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     21, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_ECCCLK] =
+		ast2700_clk_hw_register_gate(NULL, "eccclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     23, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_RSACLK] =
+		ast2700_clk_hw_register_gate(NULL, "rsaclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     24, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_RVAS0CLK] =
+		ast2700_clk_hw_register_gate(NULL, "rvasclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     25, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_UFSCLK] =
+		ast2700_clk_hw_register_gate(NULL, "ufsclk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     26, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_EMMCMUX] =
+		clk_hw_register_mux(NULL, "emmcsrc-mux", emmcclk_sel, ARRAY_SIZE(emmcclk_sel),
+				    0, clk_base + SCU0_CLK_SEL1,
+				    11, 1, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_EMMC] =
+		clk_hw_register_divider_table(NULL, "emmcclk", "emmcsrc-mux",
+					      0, clk_base + SCU0_CLK_SEL1,
+					      12, 3, 0, ast2700_clk_div_table2,
+					      &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_EMMCCLK] =
+		ast2700_clk_hw_register_gate(NULL, "emmcclk-gate", "emmcclk",
+					     0, clk_base + SCU0_CLK_STOP,
+					     27, 0, &ast2700_clk_lock);
+
+	clks[SCU0_CLK_GATE_RVAS1CLK] =
+		ast2700_clk_hw_register_gate(NULL, "rvas2clk", NULL,
+					     0, clk_base + SCU0_CLK_STOP,
+					     28, 0, &ast2700_clk_lock);
+
+	of_clk_add_hw_provider(soc0_node, of_clk_hw_onecell_get, clk_data);
+
+	return 0;
+};
+
+CLK_OF_DECLARE_DRIVER(ast2700_soc0, "aspeed,ast2700-scu0", ast2700_soc0_clk_init);
+CLK_OF_DECLARE_DRIVER(ast2700_soc1, "aspeed,ast2700-scu1", ast2700_soc1_clk_init);
-- 
2.34.1

[PATCH v1 04/10] dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset

[Kevin Chen]

---
 .../dt-bindings/reset/aspeed,ast2700-reset.h  | 126 ++++++++++++++++++
 1 file changed, 126 insertions(+)
 create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h

diff --git a/include/dt-bindings/reset/aspeed,ast2700-reset.h b/include/dt-bindings/reset/aspeed,ast2700-reset.h
new file mode 100644
index 000000000000..704cdaac3fdc
--- /dev/null
+++ b/include/dt-bindings/reset/aspeed,ast2700-reset.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 reset controller.
+ *
+ * Copyright (c) 2023 Aspeed Technology Inc.
+ */
+
+#ifndef _MACH_ASPEED_AST2700_RESET_H_
+#define _MACH_ASPEED_AST2700_RESET_H_
+
+/* SOC0 */
+#define SCU0_RESET_SDRAM		(0)
+#define SCU0_RESET_DDRPHY		(1)
+#define SCU0_RESET_RSA		(2)
+#define SCU0_RESET_SHA3		(3)
+#define SCU0_RESET_HACE		(4)
+#define SCU0_RESET_SOC		(5)
+#define SCU0_RESET_VIDEO		(6)
+#define SCU0_RESET_2D			(7)
+#define SCU0_RESET_PCIS		(8)
+#define SCU0_RESET_RVAS0		(9)
+#define SCU0_RESET_RVAS1		(10)
+#define SCU0_RESET_SM3		(11)
+#define SCU0_RESET_SM4		(12)
+#define SCU0_RESET_CRT0		(13)
+#define SCU0_RESET_ECC		(14)
+#define SCU0_RESET_DP_PCI		(15)
+#define SCU0_RESET_UFS		(16)
+#define SCU0_RESET_EMMC		(17)
+#define SCU0_RESET_PCIE1RST		(18)
+#define SCU0_RESET_PCIE1RSTOE		(19)
+#define SCU0_RESET_PCIE0RST		(20)
+#define SCU0_RESET_PCIE0RSTOE		(21)
+#define SCU0_RESET_JTAG0		(22)
+#define SCU0_RESET_MCTP0		(23)
+#define SCU0_RESET_MCTP1		(24)
+#define SCU0_RESET_XDMA0		(25)
+#define SCU0_RESET_XDMA1		(26)
+#define SCU0_RESET_H2X1		(27)
+#define SCU0_RESET_DP			(28)
+#define SCU0_RESET_DP_MCU		(29)
+#define SCU0_RESET_GP_MCU		(30)
+#define SCU0_RESET_H2X0		(31)
+#define SCU0_RESET_P0_VHUB2		(32)
+#define SCU0_RESET_P0_PHY3		(33)
+#define SCU0_RESET_P0_XHCI		(34)
+#define SCU0_RESET_P1_VHUB2		(35)
+#define SCU0_RESET_P1_PHY3		(36)
+#define SCU0_RESET_P1_XHCI		(37)
+#define SCU0_RESET_P0_USB2		(38)
+#define SCU0_RESET_P1_USB2		(39)
+#define SCU0_RESET_USB11		(40)
+#define SCU0_RESET_RESERVED		(41)
+#define SCU0_RESET_E2M0		(42)
+#define SCU0_RESET_E2M1		(43)
+
+#define SOC0_RESET_NUMS		(SCU0_RESET_E2M1 + 1)
+
+/* SOC1 */
+#define SCU1_RESET_LPC0		(0)
+#define SCU1_RESET_LPC1		(1)
+#define SCU1_RESET_MII		(2)
+#define SCU1_RESET_PECI		(3)
+#define SCU1_RESET_PWM		(4)
+#define SCU1_RESET_MAC0		(5)
+#define SCU1_RESET_MAC1		(6)
+#define SCU1_RESET_MAC2		(7)
+#define SCU1_RESET_ADC		(8)
+#define SCU1_RESET_SD			(9)
+#define SCU1_RESET_ESPI0		(10)
+#define SCU1_RESET_ESPI1		(11)
+#define SCU1_RESET_JTAG1		(12)
+#define SCU1_RESET_SPI0		(13)
+#define SCU1_RESET_SPI1		(14)
+#define SCU1_RESET_SPI2		(15)
+#define SCU1_RESET_I3C0		(16)
+#define SCU1_RESET_I3C1		(17)
+#define SCU1_RESET_I3C2		(18)
+#define SCU1_RESET_I3C3		(19)
+#define SCU1_RESET_I3C4		(20)
+#define SCU1_RESET_I3C5		(21)
+#define SCU1_RESET_I3C6		(22)
+#define SCU1_RESET_I3C7		(23)
+#define SCU1_RESET_I3C8		(24)
+#define SCU1_RESET_I3C9		(25)
+#define SCU1_RESET_I3C10		(26)
+#define SCU1_RESET_I3C11		(27)
+#define SCU1_RESET_I3C12		(28)
+#define SCU1_RESET_I3C13		(29)
+#define SCU1_RESET_I3C14		(30)
+#define SCU1_RESET_I3C15		(31)
+/* reserved 32 */
+#define SCU1_RESET_IOMCU		(33)
+#define SCU1_RESET_H2A_SPI1		(34)
+#define SCU1_RESET_H2A_SPI2		(35)
+#define SCU1_RESET_UART0		(36)
+#define SCU1_RESET_UART1		(37)
+#define SCU1_RESET_UART2		(38)
+#define SCU1_RESET_UART3		(39)
+#define SCU1_RESET_I2C_FILTER		(40)
+#define SCU1_RESET_CALIPTRA		(41)
+/* reserved 42:43 */
+#define SCU1_RESET_FSI		(44)
+#define SCU1_RESET_CAN		(45)
+#define SCU1_RESET_MCTP		(46)
+#define SCU1_RESET_I2C		(47)
+#define SCU1_RESET_UART6		(48)
+#define SCU1_RESET_UART7		(49)
+#define SCU1_RESET_UART8		(50)
+#define SCU1_RESET_UART9		(51)
+#define SCU1_RESET_LTPI		(52)
+#define SCU1_RESET_VGAL		(53)
+#define SCU1_RESET_LTPI1		(54)
+#define SCU1_RESET_ACE		(55)
+#define SCU1_RESET_E2M2		(56)
+#define SCU1_RESET_UHCI		(57)
+#define SCU1_RESET_PORTC_USB2H	(58)
+#define SCU1_RESET_PORTC_USB2V	(59)
+#define SCU1_RESET_PORTD_USB2H	(60)
+#define SCU1_RESET_PORTD_USB2V	(61)
+#define SCU1_RESET_H2X2		(62)
+#define SCU1_RESET_I3CDMA             (63)
+
+#define SOC1_RESET_NUMS		(SCU1_RESET_I3CDMA + 1)
+
+#endif  /* _MACH_ASPEED_AST2700_RESET_H_ */
-- 
2.34.1

[PATCH v1 05/10] dt-bindings: arm: aspeed: Add maintainer

[Kevin Chen]

---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 95113df178cc..71c31c08a8ad 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -8,6 +8,7 @@ title: Aspeed SoC based boards
 
 maintainers:
   - Joel Stanley <joel@jms.id.au>
+  - Kevin Chen <kevin_chen@aspeedtech.com>
 
 properties:
   $nodename:
-- 
2.34.1

[PATCH v1 06/10] dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string

[Kevin Chen]

---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 71c31c08a8ad..b21551817f44 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -99,4 +99,9 @@ properties:
               - ufispace,ncplite-bmc
           - const: aspeed,ast2600
 
+      - description: AST2700 based boards
+        items:
+          - enum:
+              - aspeed,ast2700-evb
+
 additionalProperties: true
-- 
2.34.1

[PATCH v1 07/10] arm64: aspeed: Add support for ASPEED AST2700 BMC SoC

[Kevin Chen]

---
 MAINTAINERS                  |  3 +++
 arch/arm64/Kconfig.platforms | 14 ++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c0a3d9e93689..08609430cfe0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2121,7 +2121,10 @@ Q:	https://patchwork.ozlabs.org/project/linux-aspeed/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git
 F:	Documentation/devicetree/bindings/arm/aspeed/
 F:	arch/arm/boot/dts/aspeed/
+F:	arch/arm64/boot/dts/aspeed/
 F:	arch/arm/mach-aspeed/
+F:	include/dt-bindings/clock/aspeed,ast2700-clk.h
+F:	include/dt-bindings/reset/aspeed,ast2700-reset.h
 N:	aspeed
 
 ARM/AXM LSI SOC
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6c6d11536b42..1db7b6f1ee0a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,20 @@ config ARCH_APPLE
 	  This enables support for Apple's in-house ARM SoC family, starting
 	  with the Apple M1.
 
+config ARCH_ASPEED
+	bool "Aspeed SoC family"
+	select MACH_ASPEED_G7
+	help
+	  Say yes if you intend to run on an Aspeed ast2700 or similar
+	  seventh generation Aspeed BMCs.
+
+config MACH_ASPEED_G7
+	bool "Aspeed SoC AST2700"
+	help
+	  Say yes if you intend to run on an Aspeed ast2700
+	  seventh generation Aspeed BMCs.
+	  Aspeed ast2700 BMC based on the Cortex A35.
+
 menuconfig ARCH_BCM
 	bool "Broadcom SoC Support"
 
-- 
2.34.1

[PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree

[Kevin Chen]

---
 arch/arm64/boot/dts/Makefile              |   1 +
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 217 ++++++++++++++++++++++
 2 files changed, 218 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 21cd3a87f385..c909c19dc5dd 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -34,3 +34,4 @@ subdir-y += tesla
 subdir-y += ti
 subdir-y += toshiba
 subdir-y += xilinx
+subdir-y += aspeed
diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
new file mode 100644
index 000000000000..858ab95251e4
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <dt-bindings/clock/aspeed,ast2700-clk.h>
+#include <dt-bindings/reset/aspeed,ast2700-reset.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
+
+/ {
+	model = "Aspeed BMC";
+	compatible = "aspeed,ast2700";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial12 = &uart12;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			device_type = "cpu";
+			reg = <1>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			device_type = "cpu";
+			reg = <2>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			device_type = "cpu";
+			reg = <3>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a35-pmu";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	gic: interrupt-controller@12200000 {
+		compatible = "arm,gic-v3";
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#redistributor-regions = <1>;
+		reg =	<0 0x12200000 0 0x10000>,		//GICD
+			<0 0x12280000 0 0x80000>,		//GICR
+			<0 0x40440000 0 0x1000>;		//GICC
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+	};
+
+	soc0: soc@10000000 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		soc0_sram: sram@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x0 0x10000000 0x0 0x20000>;	/* 128KiB SRAM on soc0 */
+			ranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			no-memory-wc;
+
+			exported@0 {
+				reg = <0 0x0 0 0x20000>;
+				export;
+			};
+		};
+
+		syscon0: syscon@12c02000 {
+			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+			reg = <0x0 0x12c02000 0x0 0x1000>;
+			ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+
+			silicon-id@0 {
+				compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id";
+				reg = <0 0x0 0 0x4>;
+			};
+
+			scu_ic0: interrupt-controller@1D0 {
+				#interrupt-cells = <1>;
+				compatible = "aspeed,ast2700-scu-ic0";
+				reg = <0 0x1d0 0 0xc>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+			};
+
+			scu_ic1: interrupt-controller@1E0 {
+				#interrupt-cells = <1>;
+				compatible = "aspeed,ast2700-scu-ic1";
+				reg = <0 0x1e0 0 0xc>;
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+			};
+
+			soc0_rst: reset-controller@200 {
+				reg = <0 0x200 0 0x40>;
+			};
+
+			soc0_clk: clock-controller@240 {
+				reg = <0 0x240 0 0x1c0>;
+			};
+		};
+
+	};
+
+	soc1: soc@14000000 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		syscon1: syscon@14c02000 {
+			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
+			reg = <0x0 0x14c02000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+
+			soc1_rst: reset-controller@200 {
+				#reset-cells = <1>;
+			};
+
+			soc1_clk: clock-controller@240 {
+				reg = <0 0x240 0 0x1c0>;
+			};
+		};
+
+		uart12: serial@14c33b00 {
+			compatible = "ns16550a";
+			reg = <0x0 0x14c33b00 0x0 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
+			no-loopback-test;
+			pinctrl-names = "default";
+		};
+	};
+};
+
-- 
2.34.1

[PATCH v1 09/10] arm64: dts: aspeed: Add initial AST2700 EVB device tree

[Kevin Chen]

---
 arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 50 ++++++++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts

diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile
new file mode 100644
index 000000000000..ffe7e15017cc
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_ASPEED) += \
+	ast2700-evb.dtb
diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
new file mode 100644
index 000000000000..187c458e566b
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include "aspeed-g7.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "AST2700A1-EVB";
+	compatible = "aspeed,ast2700a1-evb", "aspeed,ast2700";
+
+	chosen {
+		bootargs = "console=ttyS12,115200n8";
+		stdout-path = &uart12;
+	};
+
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	memory@400000000 {
+		device_type = "memory";
+		reg = <0x4 0x00000000 0x0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mcu_fw: mcu-firmware@42fe00000 {
+			reg = <0x4 0x2fe00000 0x0 0x200000>;
+			no-map;
+		};
+
+		atf: trusted-firmware-a@430000000 {
+			reg = <0x4 0x30000000 0x0 0x80000>;
+			no-map;
+		};
+
+		optee_core: optee_core@430080000 {
+			reg = <0x4 0x30080000 0x0 0x1000000>;
+			no-map;
+		};
+	};
+};
+
-- 
2.34.1

[PATCH v1 10/10] arm64: defconfig: Add ASPEED AST2700 family support

[Kevin Chen]

---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d32fca64996..b393735a695f 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_ASPEED=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM_IPROC=y
-- 
2.34.1

Re: [PATCH v1 01/10] dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

Missing commit msg.

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

A nit, subject: drop second/last, redundant "bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18



Best regards,
Krzysztof

Re: [PATCH v1 02/10] dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

Missing commit msg.

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters



> ---
>  .../dt-bindings/clock/aspeed,ast2700-clk.h    | 180 ++++++++++++++++++

This is supposed to be part of bindings adding the clock controller.

>  1 file changed, 180 insertions(+)
>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
> 
> diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> new file mode 100644
> index 000000000000..5ca85503736d
> --- /dev/null
> +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> @@ -0,0 +1,180 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Device Tree binding constants for AST2700 clock controller.
> + *
> + * Copyright (c) 2023 Aspeed Technology Inc.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_AST2700_H
> +#define __DT_BINDINGS_CLOCK_AST2700_H
> +
> +/* SOC0 clk-gate */
> +#define SCU0_CLK_GATE_MCLK	(0)
> +#define SCU0_CLK_GATE_ECLK	(1)

Drop all (). Not needed, not useful.

> +#define SCU0_CLK_GATE_GCLK	(2)
> +#define SCU0_CLK_GATE_VCLK	(3)
> +#define SCU0_CLK_GATE_BCLK	(4)
> +#define SCU0_CLK_GATE_D1CLK	(5)
> +#define SCU0_CLK_GATE_REFCLK	(6)
> +#define SCU0_CLK_GATE_USB0CLK	(7)
> +#define SCU0_CLK_GATE_RSV8	(8)
> +#define SCU0_CLK_GATE_USB1CLK	(9)
> +#define SCU0_CLK_GATE_D2CLK	(10)
> +#define SCU0_CLK_GATE_RSV11	(11)
> +#define SCU0_CLK_GATE_RSV12	(12)
> +#define SCU0_CLK_GATE_YCLK	(13)
> +#define SCU0_CLK_GATE_USB2CLK	(14)
> +#define SCU0_CLK_GATE_UART4CLK	(15)
> +#define SCU0_CLK_GATE_SLICLK	(16)
> +#define SCU0_CLK_GATE_DACCLK	(17)
> +#define SCU0_CLK_GATE_DP	(18)
> +#define SCU0_CLK_GATE_RSV19	(19)
> +#define SCU0_CLK_GATE_CRT1CLK	(20)
> +#define SCU0_CLK_GATE_CRT2CLK	(21)
> +#define SCU0_CLK_GATE_VLCLK	(22)
> +#define SCU0_CLK_GATE_ECCCLK	(23)
> +#define SCU0_CLK_GATE_RSACLK	(24)
> +#define SCU0_CLK_GATE_RVAS0CLK	(25)
> +#define SCU0_CLK_GATE_UFSCLK	(26)
> +#define SCU0_CLK_GATE_EMMCCLK	(27)
> +#define SCU0_CLK_GATE_RVAS1CLK	(28)
> +/* reserved 29 ~ 31*/

IDs cannot be reserved. It is a binding, not a hardware number.

> +#define SOC0_CLK_GATE_NUM	(SCU0_CLK_GATE_RVAS1CLK + 1)

No drop. Others as well.

Best regards,
Krzysztof

Re: [PATCH v1 03/10] clk: ast2700: add clock controller

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

So you did not write commit msgs to none of the commits?

> ---
>  drivers/clk/Makefile      |    1 +
>  drivers/clk/clk-ast2700.c | 1166 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 1167 insertions(+)
>  create mode 100644 drivers/clk/clk-ast2700.c
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index f793a16cad40..0d5992ea0fa4 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI)	+= clk-fsl-sai.o
>  obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o
>  obj-$(CONFIG_COMMON_CLK_ASPEED)		+= clk-aspeed.o
>  obj-$(CONFIG_MACH_ASPEED_G6)		+= clk-ast2600.o
> +obj-$(CONFIG_MACH_ASPEED_G7)		+= clk-ast2700.o

...

> +
> +static const char *const pspclk_sel[] = {
> +	"soc0-mpll",
> +	"soc0-hpll",
> +};
> +
> +static const char *const soc0_uartclk_sel[] = {
> +	"soc0-clk24Mhz",
> +	"soc0-clk192Mhz",
> +};
> +
> +static const char *const emmcclk_sel[] = {
> +	"soc0-mpll_div4",
> +	"soc0-hpll_div4",
> +};
> +
> +static int ast2700_soc0_clk_init(struct device_node *soc0_node)
> +{
> +	struct clk_hw_onecell_data *clk_data;
> +	void __iomem *clk_base;
> +	struct ast2700_reset *reset;
> +	struct clk_hw **clks;
> +	int div;
> +	u32 val;
> +	int ret;
> +
> +	clk_data = kzalloc(struct_size(clk_data, hws, SOC0_NUM_CLKS), GFP_KERNEL);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	clk_data->num = SOC0_NUM_CLKS;
> +	clks = clk_data->hws;
> +
> +	clk_base = of_iomap(soc0_node, 0);
> +	if (WARN_ON(IS_ERR(clk_base)))

Drop WARN_ON

> +		return PTR_ERR(clk_base);
> +
> +	reset = kzalloc(sizeof(*reset), GFP_KERNEL);
> +	if (!reset)
> +		return -ENOMEM;
> +
> +	reset->base = clk_base;
> +
> +	reset->rcdev.owner = THIS_MODULE;
> +	reset->rcdev.nr_resets = SOC0_RESET_NUMS;
> +	reset->rcdev.ops = &ast2700_reset_ops;
> +	reset->rcdev.of_node = soc0_node;
> +
> +	ret = reset_controller_register(&reset->rcdev);
> +	if (ret) {
> +		pr_err("soc0 failed to register reset controller\n");
> +		return ret;
> +	}
> +
> +	//refclk

Weird comment. Please read Coding Style.


> +	clks[SCU0_CLKIN] =
> +		clk_hw_register_fixed_rate(NULL, "soc0-clkin", NULL, 0, SCU_CLK_25MHZ);
> +
> +	clks[SCU0_CLK_24M] =
> +		clk_hw_register_fixed_rate(NULL, "soc0-clk24Mhz", NULL, 0, SCU_CLK_24MHZ);
> +
> +	clks[SCU0_CLK_192M] =
> +		clk_hw_register_fixed_rate(NULL, "soc0-clk192Mhz", NULL, 0, SCU_CLK_192MHZ);
> +
> +	//hpll
> +	val = readl(clk_base + SCU0_HWSTRAP1);
> +	if ((val & GENMASK(3, 2)) != 0) {
> +		switch ((val & GENMASK(3, 2)) >> 2) {
> +		case 1:
> +			clks[SCU0_CLK_HPLL] =
> +				clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1900000000);
> +			break;
> +		case 2:
> +			clks[SCU0_CLK_HPLL] =
> +				clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1800000000);
> +			break;
> +		case 3:
> +			clks[SCU0_CLK_HPLL] =
> +				clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1700000000);
> +			break;
> +		}
> +	} else {
> +		val = readl(clk_base + SCU0_HPLL_PARAM);
> +		clks[SCU0_CLK_HPLL] = ast2700_soc0_hw_pll("soc0-hpll", "soc0-clkin", val);
> +	}
> +	clks[SCU0_CLK_HPLL_DIV2] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div2", "soc0-hpll", 0, 1, 2);
> +	clks[SCU0_CLK_HPLL_DIV4] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div4", "soc0-hpll", 0, 1, 4);
> +
> +	//dpll



Best regards,
Krzysztof

Re: [PATCH v1 04/10] dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> ---

Sorry, that's not acceptable. This does not have even SoB.

All previous comments apply.

Best regards,
Krzysztof

Re: [PATCH v1 05/10] dt-bindings: arm: aspeed: Add maintainer

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:

Why?

> ---
>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
>  1 file changed, 1 insertion(+)
Best regards,
Krzysztof

Re: [PATCH v1 06/10] dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> ---
>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> index 71c31c08a8ad..b21551817f44 100644
> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> @@ -99,4 +99,9 @@ properties:
>                - ufispace,ncplite-bmc
>            - const: aspeed,ast2600
>  
> +      - description: AST2700 based boards
> +        items:
> +          - enum:
> +              - aspeed,ast2700-evb

NAK, this cannot be alone. Look at all other examples. Why are you doing
things differently?

Best regards,
Krzysztof

Re: [PATCH v1 07/10] arm64: aspeed: Add support for ASPEED AST2700 BMC SoC

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> ---
>  MAINTAINERS                  |  3 +++
>  arch/arm64/Kconfig.platforms | 14 ++++++++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c0a3d9e93689..08609430cfe0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2121,7 +2121,10 @@ Q:	https://patchwork.ozlabs.org/project/linux-aspeed/list/
>  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git
>  F:	Documentation/devicetree/bindings/arm/aspeed/
>  F:	arch/arm/boot/dts/aspeed/
> +F:	arch/arm64/boot/dts/aspeed/
>  F:	arch/arm/mach-aspeed/
> +F:	include/dt-bindings/clock/aspeed,ast2700-clk.h
> +F:	include/dt-bindings/reset/aspeed,ast2700-reset.h
>  N:	aspeed
>  
>  ARM/AXM LSI SOC
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6c6d11536b42..1db7b6f1ee0a 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -40,6 +40,20 @@ config ARCH_APPLE
>  	  This enables support for Apple's in-house ARM SoC family, starting
>  	  with the Apple M1.
>  
> +config ARCH_ASPEED
> +	bool "Aspeed SoC family"
> +	select MACH_ASPEED_G7
> +	help
> +	  Say yes if you intend to run on an Aspeed ast2700 or similar
> +	  seventh generation Aspeed BMCs.
> +
> +config MACH_ASPEED_G7
> +	bool "Aspeed SoC AST2700"

There are no MACHines for arm64. Look at this code. Do you see MACH
anywhere else? No. Then why Aspeed must be different?

No. Drop.

Best regards,
Krzysztof

Re: [PATCH v1 09/10] arm64: dts: aspeed: Add initial AST2700 EVB device tree

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> ---
>  arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
>  arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 50 ++++++++++++++++++++++
>  2 files changed, 54 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
>  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> 
> diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile
> new file mode 100644
> index 000000000000..ffe7e15017cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/aspeed/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_ASPEED) += \
> +	ast2700-evb.dtb
> diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> new file mode 100644
> index 000000000000..187c458e566b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +/dts-v1/;
> +
> +#include "aspeed-g7.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +
> +/ {
> +	model = "AST2700A1-EVB";
> +	compatible = "aspeed,ast2700a1-evb", "aspeed,ast2700";

You have never tested this.

Sorry, test your DTS first.

> +
> +	chosen {
> +		bootargs = "console=ttyS12,115200n8";

Drop.

> +		stdout-path = &uart12;
> +	};
> +
> +	firmware {
> +		optee: optee {
> +			compatible = "linaro,optee-tz";
> +			method = "smc";
> +		};
> +	};
> +
> +	memory@400000000 {
> +		device_type = "memory";
> +		reg = <0x4 0x00000000 0x0 0x40000000>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		mcu_fw: mcu-firmware@42fe00000 {
> +			reg = <0x4 0x2fe00000 0x0 0x200000>;
> +			no-map;
> +		};
> +
> +		atf: trusted-firmware-a@430000000 {
> +			reg = <0x4 0x30000000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		optee_core: optee_core@430080000 {

Read DTS coding style.

> +			reg = <0x4 0x30080000 0x0 0x1000000>;
> +			no-map;
> +		};
> +	};
> +};
> +

Remove stray blank line.

Best regards,
Krzysztof

Re: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree

[Krzysztof Kozlowski]

On 26/07/2024 13:03, Kevin Chen wrote:
> ---
>  arch/arm64/boot/dts/Makefile              |   1 +
>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 217 ++++++++++++++++++++++
>  2 files changed, 218 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 21cd3a87f385..c909c19dc5dd 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -34,3 +34,4 @@ subdir-y += tesla
>  subdir-y += ti
>  subdir-y += toshiba
>  subdir-y += xilinx
> +subdir-y += aspeed
> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> new file mode 100644
> index 000000000000..858ab95251e4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +#include <dt-bindings/clock/aspeed,ast2700-clk.h>
> +#include <dt-bindings/reset/aspeed,ast2700-reset.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> +
> +/ {
> +	model = "Aspeed BMC";

Model of what? No, drop.

> +	compatible = "aspeed,ast2700";

Please run scripts/checkpatch.pl and fix reported warnings. Then please
run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
Some warnings can be ignored, especially from --strict run, but the code
here looks like it needs a fix. Feel free to get in touch if the warning
is not clear.


> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		serial12 = &uart12;

Nope. Such aliases are board specific.

> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			device_type = "cpu";
> +			reg = <0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			device_type = "cpu";
> +			reg = <1>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			device_type = "cpu";
> +			reg = <2>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			device_type = "cpu";
> +			reg = <3>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-size = <0x80000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a35-pmu";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	psci {

Order the nodes according to DTS coding style.

Fix all your patches:
1. To pass flawlessly checkpatch (you did not run it)
2. To pass dt_binding_check and dtbs_check (you did not run these)
3. To adhere to kernel coding style
4. To adhere to DTS coding style

> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	gic: interrupt-controller@12200000 {

Nope, this cannot be outside of SoC.

> +		compatible = "arm,gic-v3";
> +		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		interrupt-parent = <&gic>;
> +		#redistributor-regions = <1>;
> +		reg =	<0 0x12200000 0 0x10000>,		//GICD
> +			<0 0x12280000 0 0x80000>,		//GICR
> +			<0 0x40440000 0 0x1000>;		//GICC

Read DTS coding style and order this correctly.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +		arm,cpu-registers-not-fw-configured;
> +		always-on;
> +	};
> +
> +	soc0: soc@10000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		soc0_sram: sram@10000000 {
> +			compatible = "mmio-sram";
> +			reg = <0x0 0x10000000 0x0 0x20000>;	/* 128KiB SRAM on soc0 */
> +			ranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			no-memory-wc;
> +
> +			exported@0 {
> +				reg = <0 0x0 0 0x20000>;
> +				export;
> +			};
> +		};
> +
> +		syscon0: syscon@12c02000 {
> +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
> +			reg = <0x0 0x12c02000 0x0 0x1000>;
> +			ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +
> +			silicon-id@0 {
> +				compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id";
> +				reg = <0 0x0 0 0x4>;
> +			};
> +
> +			scu_ic0: interrupt-controller@1D0 {

DTS coding style...

> +				#interrupt-cells = <1>;
> +				compatible = "aspeed,ast2700-scu-ic0";
> +				reg = <0 0x1d0 0 0xc>;
> +				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-controller;
> +			};
> +
> +			scu_ic1: interrupt-controller@1E0 {
> +				#interrupt-cells = <1>;
> +				compatible = "aspeed,ast2700-scu-ic1";
> +				reg = <0 0x1e0 0 0xc>;
> +				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-controller;
> +			};
> +
> +			soc0_rst: reset-controller@200 {
> +				reg = <0 0x200 0 0x40>;
> +			};
> +
> +			soc0_clk: clock-controller@240 {
> +				reg = <0 0x240 0 0x1c0>;
> +			};
> +		};
> +
> +	};
> +
> +	soc1: soc@14000000 {

Wait, what, to socs?

> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		syscon1: syscon@14c02000 {
> +			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
> +			reg = <0x0 0x14c02000 0x0 0x1000>;
> +			ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +
> +			soc1_rst: reset-controller@200 {
> +				#reset-cells = <1>;
> +			};
> +
> +			soc1_clk: clock-controller@240 {
> +				reg = <0 0x240 0 0x1c0>;
> +			};
> +		};
> +
> +		uart12: serial@14c33b00 {
> +			compatible = "ns16550a";
> +			reg = <0x0 0x14c33b00 0x0 0x100>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
> +			no-loopback-test;
> +			pinctrl-names = "default";

What is this?

> +		};
> +	};
> +};
> +

Best regards,
Krzysztof

Re: [PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC

[Rob Herring (Arm)]

On Fri, 26 Jul 2024 19:03:45 +0800, Kevin Chen wrote:
> This patchset adds initial support for the ASPEED.
> AST27XX Board Management controller (BMC) SoC family.
> 
> AST2700 is ASPEED's 8th-generation server management processor.
> Featuring a quad-core ARM Cortex A35 64-bit processor and two
> independent ARM Cortex M4 processors
> 
> This patchset adds minimal architecture and drivers such as:
> Clocksource, Clock and Reset
> 
> This patchset was tested on the ASPEED AST2700 evaluation board.
> 
> Kevin Chen (10):
>   dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700
>     SCU
>   dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock
>   clk: ast2700: add clock controller
>   dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset
>   dt-bindings: arm: aspeed: Add maintainer
>   dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string
>   arm64: aspeed: Add support for ASPEED AST2700 BMC SoC
>   arm64: dts: aspeed: Add initial AST27XX device tree
>   arm64: dts: aspeed: Add initial AST2700 EVB device tree
>   arm64: defconfig: Add ASPEED AST2700 family support
> 
>  .../bindings/arm/aspeed/aspeed.yaml           |    6 +
>  .../bindings/mfd/aspeed,ast2x00-scu.yaml      |    3 +
>  MAINTAINERS                                   |    3 +
>  arch/arm64/Kconfig.platforms                  |   14 +
>  arch/arm64/boot/dts/Makefile                  |    1 +
>  arch/arm64/boot/dts/aspeed/Makefile           |    4 +
>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     |  217 +++
>  arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |   50 +
>  arch/arm64/configs/defconfig                  |    1 +
>  drivers/clk/Makefile                          |    1 +
>  drivers/clk/clk-ast2700.c                     | 1166 +++++++++++++++++
>  .../dt-bindings/clock/aspeed,ast2700-clk.h    |  180 +++
>  .../dt-bindings/reset/aspeed,ast2700-reset.h  |  126 ++
>  13 files changed, 1772 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
>  create mode 100644 drivers/clk/clk-ast2700.c
>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
> 
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y aspeed/ast2700-evb.dtb' for 20240726110355.2181563-1-kevin_chen@aspeedtech.com:

arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: /: failed to match any schema with compatible: ['aspeed,ast2700a1-evb', 'aspeed,ast2700']
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: /: failed to match any schema with compatible: ['aspeed,ast2700a1-evb', 'aspeed,ast2700']
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: l2-cache0: 'cache-unified' is a dependency of 'cache-size'
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: l2-cache0: 'cache-unified' is a dependency of 'cache-sets'
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: l2-cache0: 'cache-unified' is a dependency of 'cache-line-size'
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: l2-cache0: 'cache-unified' is a required property
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: l2-cache0: Unevaluated properties are not allowed ('cache-level', 'cache-line-size', 'cache-sets', 'cache-size' were unexpected)
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: sram@10000000: #address-cells: 1 was expected
	from schema $id: http://devicetree.org/schemas/sram/sram.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: sram@10000000: #size-cells: 1 was expected
	from schema $id: http://devicetree.org/schemas/sram/sram.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: sram@10000000: 'exported@0' does not match any of the regexes: '^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$', 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sram/sram.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: /soc@10000000/syscon@12c02000: failed to match any schema with compatible: ['aspeed,ast2700-scu0', 'syscon', 'simple-mfd']
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: /soc@10000000/syscon@12c02000/interrupt-controller@1D0: failed to match any schema with compatible: ['aspeed,ast2700-scu-ic0']
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: /soc@10000000/syscon@12c02000/interrupt-controller@1E0: failed to match any schema with compatible: ['aspeed,ast2700-scu-ic1']
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: /soc@14000000/syscon@14c02000: failed to match any schema with compatible: ['aspeed,ast2700-scu1', 'syscon', 'simple-mfd']
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: serial@14c33b00: 'oneOf' conditional failed, one must be fixed:
	'interrupts' is a required property
	'interrupts-extended' is a required property
	from schema $id: http://devicetree.org/schemas/serial/8250.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: serial@14c33b00: 'pinctrl-0' is a dependency of 'pinctrl-names'
	from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#

Re: [PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC

[Krzysztof Kozlowski]

On 26/07/2024 15:09, Rob Herring (Arm) wrote:
> 
> On Fri, 26 Jul 2024 19:03:45 +0800, Kevin Chen wrote:
>> This patchset adds initial support for the ASPEED.
>> AST27XX Board Management controller (BMC) SoC family.
>>
>> AST2700 is ASPEED's 8th-generation server management processor.
>> Featuring a quad-core ARM Cortex A35 64-bit processor and two
>> independent ARM Cortex M4 processors
>>
>> This patchset adds minimal architecture and drivers such as:
>> Clocksource, Clock and Reset
>>
>> This patchset was tested on the ASPEED AST2700 evaluation board.
>>
>> Kevin Chen (10):
>>   dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700
>>     SCU
>>   dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock
>>   clk: ast2700: add clock controller
>>   dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset
>>   dt-bindings: arm: aspeed: Add maintainer
>>   dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string
>>   arm64: aspeed: Add support for ASPEED AST2700 BMC SoC
>>   arm64: dts: aspeed: Add initial AST27XX device tree
>>   arm64: dts: aspeed: Add initial AST2700 EVB device tree
>>   arm64: defconfig: Add ASPEED AST2700 family support
>>
>>  .../bindings/arm/aspeed/aspeed.yaml           |    6 +
>>  .../bindings/mfd/aspeed,ast2x00-scu.yaml      |    3 +
>>  MAINTAINERS                                   |    3 +
>>  arch/arm64/Kconfig.platforms                  |   14 +
>>  arch/arm64/boot/dts/Makefile                  |    1 +
>>  arch/arm64/boot/dts/aspeed/Makefile           |    4 +
>>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     |  217 +++
>>  arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |   50 +
>>  arch/arm64/configs/defconfig                  |    1 +
>>  drivers/clk/Makefile                          |    1 +
>>  drivers/clk/clk-ast2700.c                     | 1166 +++++++++++++++++
>>  .../dt-bindings/clock/aspeed,ast2700-clk.h    |  180 +++
>>  .../dt-bindings/reset/aspeed,ast2700-reset.h  |  126 ++
>>  13 files changed, 1772 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
>>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
>>  create mode 100644 drivers/clk/clk-ast2700.c
>>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
>>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
>>
>> --
>> 2.34.1
>>
>>
>>
> 
> 
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
> 
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
> 
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
> 
>   pip3 install dtschema --upgrade
> 
> 
> New warnings running 'make CHECK_DTBS=y aspeed/ast2700-evb.dtb' for 20240726110355.2181563-1-kevin_chen@aspeedtech.com:

Kevin,
Just to clarify. Looking at the patches it was quite obvious you did not
test it with dtbs_check. For a new arm64 platform without any legacy,
having 0 warnings is a must.

Consider Documentation/process/maintainer-soc-clean-dts.rst being
implied for this platform.

Best regards,
Krzysztof

[PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC

[Kevin Chen]

This patchset adds initial support for the ASPEED.
AST27XX Board Management controller (BMC) SoC family.

AST2700 is ASPEED's 8th-generation server management processor.
Featuring a quad-core ARM Cortex A35 64-bit processor and two
independent ARM Cortex M4 processors

This patchset adds minimal architecture and drivers such as:
Clocksource, Clock and Reset

This patchset was tested on the ASPEED AST2700 evaluation board.

Kevin Chen (10):
  dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700
    SCU
  dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock
  clk: ast2700: add clock controller
  dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset
  dt-bindings: arm: aspeed: Add maintainer
  dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string
  arm64: aspeed: Add support for ASPEED AST2700 BMC SoC
  arm64: dts: aspeed: Add initial AST27XX device tree
  arm64: dts: aspeed: Add initial AST2700 EVB device tree
  arm64: defconfig: Add ASPEED AST2700 family support

 .../bindings/arm/aspeed/aspeed.yaml           |    6 +
 .../bindings/mfd/aspeed,ast2x00-scu.yaml      |    3 +
 MAINTAINERS                                   |    3 +
 arch/arm64/Kconfig.platforms                  |   14 +
 arch/arm64/boot/dts/Makefile                  |    1 +
 arch/arm64/boot/dts/aspeed/Makefile           |    4 +
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     |  217 +++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |   50 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/clk-ast2700.c                     | 1166 +++++++++++++++++
 .../dt-bindings/clock/aspeed,ast2700-clk.h    |  180 +++
 .../dt-bindings/reset/aspeed,ast2700-reset.h  |  126 ++
 13 files changed, 1772 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
 create mode 100644 drivers/clk/clk-ast2700.c
 create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
 create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h

-- 
2.34.1

RE: [PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC

[Kevin Chen]

Hi Krzk,

I will separate clock part in the v3 patch into Ryan's clock series.

>
> On 26/07/2024 15:09, Rob Herring (Arm) wrote:
> >
> > On Fri, 26 Jul 2024 19:03:45 +0800, Kevin Chen wrote:
> >> This patchset adds initial support for the ASPEED.
> >> AST27XX Board Management controller (BMC) SoC family.
> >>
> >> AST2700 is ASPEED's 8th-generation server management processor.
> >> Featuring a quad-core ARM Cortex A35 64-bit processor and two
> >> independent ARM Cortex M4 processors
> >>
> >> This patchset adds minimal architecture and drivers such as:
> >> Clocksource, Clock and Reset
> >>
> >> This patchset was tested on the ASPEED AST2700 evaluation board.
> >>
> >> Kevin Chen (10):
> >>   dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700
> >>     SCU
> >>   dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock
> >>   clk: ast2700: add clock controller
> >>   dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset
> >>   dt-bindings: arm: aspeed: Add maintainer
> >>   dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string
> >>   arm64: aspeed: Add support for ASPEED AST2700 BMC SoC
> >>   arm64: dts: aspeed: Add initial AST27XX device tree
> >>   arm64: dts: aspeed: Add initial AST2700 EVB device tree
> >>   arm64: defconfig: Add ASPEED AST2700 family support
> >>
> >>  .../bindings/arm/aspeed/aspeed.yaml           |    6 +
> >>  .../bindings/mfd/aspeed,ast2x00-scu.yaml      |    3 +
> >>  MAINTAINERS                                   |    3 +
> >>  arch/arm64/Kconfig.platforms                  |   14 +
> >>  arch/arm64/boot/dts/Makefile                  |    1 +
> >>  arch/arm64/boot/dts/aspeed/Makefile           |    4 +
> >>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     |  217 +++
> >>  arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |   50 +
> >>  arch/arm64/configs/defconfig                  |    1 +
> >>  drivers/clk/Makefile                          |    1 +
> >>  drivers/clk/clk-ast2700.c                     | 1166
> +++++++++++++++++
> >>  .../dt-bindings/clock/aspeed,ast2700-clk.h    |  180 +++
> >>  .../dt-bindings/reset/aspeed,ast2700-reset.h  |  126 ++
> >>  13 files changed, 1772 insertions(+)  create mode 100644
> >> arch/arm64/boot/dts/aspeed/Makefile
> >>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> >>  create mode 100644 drivers/clk/clk-ast2700.c  create mode 100644
> >> include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
> >>
> >> --
> >> 2.34.1
> >>
> >>
> >>
> >
> >
> > My bot found new DTB warnings on the .dts files added or changed in
> > this series.
> >
> > Some warnings may be from an existing SoC .dtsi. Or perhaps the
> > warnings are fixed by another series. Ultimately, it is up to the
> > platform maintainer whether these warnings are acceptable or not. No
> > need to reply unless the platform maintainer has comments.
> >
> > If you already ran DT checks and didn't see these error(s), then make
> > sure dt-schema is up to date:
> >
> >   pip3 install dtschema --upgrade
> >
> >
> > New warnings running 'make CHECK_DTBS=y aspeed/ast2700-evb.dtb' for
> 20240726110355.2181563-1-kevin_chen@aspeedtech.com:
>
> Kevin,
> Just to clarify. Looking at the patches it was quite obvious you did not test it
> with dtbs_check. For a new arm64 platform without any legacy, having 0
> warnings is a must.
Agree.

>
> Consider Documentation/process/maintainer-soc-clean-dts.rst being implied
> for this platform.
>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 01/10] dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU

[Kevin Chen]

Hi Krzk,

I will separate clock part in the v3 patch into Ryan's clock series.
>
> Missing commit msg.
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory your
> patch is touching. For bindings, the preferred subjects are explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patch
> es.html#i-for-patch-submitters
>
> A nit, subject: drop second/last, redundant "bindings for". The "dt-bindings"
> prefix is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bin
> dings/submitting-patches.rst#L18
Agree, already fixed in another commit in Ryan's series.
https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-2-ryan_chen@aspeedtech.com/

>
>
>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 02/10] dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock

[Kevin Chen]

Hi Krzk,

I will separate clock part in the v3 patch into Ryan's clock series.
>
> Missing commit msg.
>
> A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix
> is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bin
> dings/submitting-patches.rst#L18
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory your
> patch is touching. For bindings, the preferred subjects are explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patch
> es.html#i-for-patch-submitters
Agree, already fixed in another commit in Ryan's series.
https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-4-ryan_chen@aspeedtech.com/

>
>
>
> > ---
> >  .../dt-bindings/clock/aspeed,ast2700-clk.h    | 180 ++++++++++++++++++
>
> This is supposed to be part of bindings adding the clock controller.
>
> >  1 file changed, 180 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
> >
> > diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h
> > b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> > new file mode 100644
> > index 000000000000..5ca85503736d
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> > @@ -0,0 +1,180 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * Device Tree binding constants for AST2700 clock controller.
> > + *
> > + * Copyright (c) 2023 Aspeed Technology Inc.
> > + */
> > +
> > +#ifndef __DT_BINDINGS_CLOCK_AST2700_H #define
> > +__DT_BINDINGS_CLOCK_AST2700_H
> > +
> > +/* SOC0 clk-gate */
> > +#define SCU0_CLK_GATE_MCLK (0)
> > +#define SCU0_CLK_GATE_ECLK (1)
>
> Drop all (). Not needed, not useful.
>
> > +#define SCU0_CLK_GATE_GCLK (2)
> > +#define SCU0_CLK_GATE_VCLK (3)
> > +#define SCU0_CLK_GATE_BCLK (4)
> > +#define SCU0_CLK_GATE_D1CLK        (5)
> > +#define SCU0_CLK_GATE_REFCLK       (6)
> > +#define SCU0_CLK_GATE_USB0CLK      (7)
> > +#define SCU0_CLK_GATE_RSV8 (8)
> > +#define SCU0_CLK_GATE_USB1CLK      (9)
> > +#define SCU0_CLK_GATE_D2CLK        (10)
> > +#define SCU0_CLK_GATE_RSV11        (11)
> > +#define SCU0_CLK_GATE_RSV12        (12)
> > +#define SCU0_CLK_GATE_YCLK (13)
> > +#define SCU0_CLK_GATE_USB2CLK      (14)
> > +#define SCU0_CLK_GATE_UART4CLK     (15)
> > +#define SCU0_CLK_GATE_SLICLK       (16)
> > +#define SCU0_CLK_GATE_DACCLK       (17)
> > +#define SCU0_CLK_GATE_DP   (18)
> > +#define SCU0_CLK_GATE_RSV19        (19)
> > +#define SCU0_CLK_GATE_CRT1CLK      (20)
> > +#define SCU0_CLK_GATE_CRT2CLK      (21)
> > +#define SCU0_CLK_GATE_VLCLK        (22)
> > +#define SCU0_CLK_GATE_ECCCLK       (23)
> > +#define SCU0_CLK_GATE_RSACLK       (24)
> > +#define SCU0_CLK_GATE_RVAS0CLK     (25)
> > +#define SCU0_CLK_GATE_UFSCLK       (26)
> > +#define SCU0_CLK_GATE_EMMCCLK      (27)
> > +#define SCU0_CLK_GATE_RVAS1CLK     (28)
> > +/* reserved 29 ~ 31*/
>
> IDs cannot be reserved. It is a binding, not a hardware number.
Agree, already fixed in another commit in Ryan's series.
https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-4-ryan_chen@aspeedtech.com/

>
> > +#define SOC0_CLK_GATE_NUM  (SCU0_CLK_GATE_RVAS1CLK + 1)
>
> No drop. Others as well.
Agree, already fixed in another commit in Ryan's series.
https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-4-ryan_chen@aspeedtech.com/

>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 03/10] clk: ast2700: add clock controller

[Kevin Chen]

Hi Krzk,

I will separate clock part in the v3 patch into Ryan's clock series.
>
> So you did not write commit msgs to none of the commits?
>
> > ---
> >  drivers/clk/Makefile      |    1 +
> >  drivers/clk/clk-ast2700.c | 1166
> > +++++++++++++++++++++++++++++++++++++
> >  2 files changed, 1167 insertions(+)
> >  create mode 100644 drivers/clk/clk-ast2700.c
> >
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > f793a16cad40..0d5992ea0fa4 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI)  += clk-fsl-sai.o
> >  obj-$(CONFIG_COMMON_CLK_GEMINI)            += clk-gemini.o
> >  obj-$(CONFIG_COMMON_CLK_ASPEED)            += clk-aspeed.o
> >  obj-$(CONFIG_MACH_ASPEED_G6)               += clk-ast2600.o
> > +obj-$(CONFIG_MACH_ASPEED_G7)               += clk-ast2700.o
>
> ...
>
> > +
> > +static const char *const pspclk_sel[] = {
> > +   "soc0-mpll",
> > +   "soc0-hpll",
> > +};
> > +
> > +static const char *const soc0_uartclk_sel[] = {
> > +   "soc0-clk24Mhz",
> > +   "soc0-clk192Mhz",
> > +};
> > +
> > +static const char *const emmcclk_sel[] = {
> > +   "soc0-mpll_div4",
> > +   "soc0-hpll_div4",
> > +};
> > +
> > +static int ast2700_soc0_clk_init(struct device_node *soc0_node) {
> > +   struct clk_hw_onecell_data *clk_data;
> > +   void __iomem *clk_base;
> > +   struct ast2700_reset *reset;
> > +   struct clk_hw **clks;
> > +   int div;
> > +   u32 val;
> > +   int ret;
> > +
> > +   clk_data = kzalloc(struct_size(clk_data, hws, SOC0_NUM_CLKS),
> GFP_KERNEL);
> > +   if (!clk_data)
> > +           return -ENOMEM;
> > +
> > +   clk_data->num = SOC0_NUM_CLKS;
> > +   clks = clk_data->hws;
> > +
> > +   clk_base = of_iomap(soc0_node, 0);
> > +   if (WARN_ON(IS_ERR(clk_base)))
>
> Drop WARN_ON
I remind Ryan for this fix. He will reply in these series.
https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-5-ryan_chen@aspeedtech.com/

>
> > +           return PTR_ERR(clk_base);
> > +
> > +   reset = kzalloc(sizeof(*reset), GFP_KERNEL);
> > +   if (!reset)
> > +           return -ENOMEM;
> > +
> > +   reset->base = clk_base;
> > +
> > +   reset->rcdev.owner = THIS_MODULE;
> > +   reset->rcdev.nr_resets = SOC0_RESET_NUMS;
> > +   reset->rcdev.ops = &ast2700_reset_ops;
> > +   reset->rcdev.of_node = soc0_node;
> > +
> > +   ret = reset_controller_register(&reset->rcdev);
> > +   if (ret) {
> > +           pr_err("soc0 failed to register reset controller\n");
> > +           return ret;
> > +   }
> > +
> > +   //refclk
>
> Weird comment. Please read Coding Style.
I remind Ryan for this fix. He will reply in these series.
https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-5-ryan_chen@aspeedtech.com/

>
>
> > +   clks[SCU0_CLKIN] =
> > +           clk_hw_register_fixed_rate(NULL, "soc0-clkin", NULL, 0,
> > +SCU_CLK_25MHZ);
> > +
> > +   clks[SCU0_CLK_24M] =
> > +           clk_hw_register_fixed_rate(NULL, "soc0-clk24Mhz", NULL, 0,
> > +SCU_CLK_24MHZ);
> > +
> > +   clks[SCU0_CLK_192M] =
> > +           clk_hw_register_fixed_rate(NULL, "soc0-clk192Mhz", NULL, 0,
> > +SCU_CLK_192MHZ);
> > +
> > +   //hpll
> > +   val = readl(clk_base + SCU0_HWSTRAP1);
> > +   if ((val & GENMASK(3, 2)) != 0) {
> > +           switch ((val & GENMASK(3, 2)) >> 2) {
> > +           case 1:
> > +                   clks[SCU0_CLK_HPLL] =
> > +                           clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0,
> 1900000000);
> > +                   break;
> > +           case 2:
> > +                   clks[SCU0_CLK_HPLL] =
> > +                           clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0,
> 1800000000);
> > +                   break;
> > +           case 3:
> > +                   clks[SCU0_CLK_HPLL] =
> > +                           clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0,
> 1700000000);
> > +                   break;
> > +           }
> > +   } else {
> > +           val = readl(clk_base + SCU0_HPLL_PARAM);
> > +           clks[SCU0_CLK_HPLL] = ast2700_soc0_hw_pll("soc0-hpll",
> "soc0-clkin", val);
> > +   }
> > +   clks[SCU0_CLK_HPLL_DIV2] = clk_hw_register_fixed_factor(NULL,
> "soc0-hpll_div2", "soc0-hpll", 0, 1, 2);
> > +   clks[SCU0_CLK_HPLL_DIV4] = clk_hw_register_fixed_factor(NULL,
> > +"soc0-hpll_div4", "soc0-hpll", 0, 1, 4);
> > +
> > +   //dpll
>
>
>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 09/10] arm64: dts: aspeed: Add initial AST2700 EVB device tree

[Kevin Chen]

Hi Krzk,

> > ---
> >  arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
> >  arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 50
> ++++++++++++++++++++++
> >  2 files changed, 54 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
> >  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> >
> > diff --git a/arch/arm64/boot/dts/aspeed/Makefile
> b/arch/arm64/boot/dts/aspeed/Makefile
> > new file mode 100644
> > index 000000000000..ffe7e15017cc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/aspeed/Makefile
> > @@ -0,0 +1,4 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +dtb-$(CONFIG_ARCH_ASPEED) += \
> > +   ast2700-evb.dtb
> > diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > new file mode 100644
> > index 000000000000..187c458e566b
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > @@ -0,0 +1,50 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +
> > +/dts-v1/;
> > +
> > +#include "aspeed-g7.dtsi"
> > +#include <dt-bindings/gpio/aspeed-gpio.h>
> > +
> > +/ {
> > +   model = "AST2700A1-EVB";
> > +   compatible = "aspeed,ast2700a1-evb", "aspeed,ast2700";
>
> You have never tested this.
>
> Sorry, test your DTS first.
Agree. I will test my dts by make dtbs_check W=1

>
> > +
> > +   chosen {
> > +           bootargs = "console=ttyS12,115200n8";
>
> Drop.
Agree.

>
> > +           stdout-path = &uart12;
> > +   };
> > +
> > +   firmware {
> > +           optee: optee {
> > +                   compatible = "linaro,optee-tz";
> > +                   method = "smc";
> > +           };
> > +   };
> > +
> > +   memory@400000000 {
> > +           device_type = "memory";
> > +           reg = <0x4 0x00000000 0x0 0x40000000>;
> > +   };
> > +
> > +   reserved-memory {
> > +           #address-cells = <2>;
> > +           #size-cells = <2>;
> > +           ranges;
> > +
> > +           mcu_fw: mcu-firmware@42fe00000 {
> > +                   reg = <0x4 0x2fe00000 0x0 0x200000>;
> > +                   no-map;
> > +           };
> > +
> > +           atf: trusted-firmware-a@430000000 {
> > +                   reg = <0x4 0x30000000 0x0 0x80000>;
> > +                   no-map;
> > +           };
> > +
> > +           optee_core: optee_core@430080000 {
>
> Read DTS coding style.
Agree. Should I change to optee_core: optee-core@430080000 {

>
> > +                   reg = <0x4 0x30080000 0x0 0x1000000>;
> > +                   no-map;
> > +           };
> > +   };
> > +};
> > +
>
> Remove stray blank line.
Agree.

>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree

[Kevin Chen]

Hi Krzk,

> > ---
> >  arch/arm64/boot/dts/Makefile              |   1 +
> >  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 217
> > ++++++++++++++++++++++
> >  2 files changed, 218 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/Makefile
> > b/arch/arm64/boot/dts/Makefile index 21cd3a87f385..c909c19dc5dd
> 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -34,3 +34,4 @@ subdir-y += tesla
> >  subdir-y += ti
> >  subdir-y += toshiba
> >  subdir-y += xilinx
> > +subdir-y += aspeed
> > diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > new file mode 100644
> > index 000000000000..858ab95251e4
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > @@ -0,0 +1,217 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later #include
> > +<dt-bindings/clock/aspeed,ast2700-clk.h>
> > +#include <dt-bindings/reset/aspeed,ast2700-reset.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> > +
> > +/ {
> > +   model = "Aspeed BMC";
>
> Model of what? No, drop.
Can I change to "model = "AST2700 EVB""

>
> > +   compatible = "aspeed,ast2700";
>
> Please run scripts/checkpatch.pl and fix reported warnings. Then please run
> `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
> Some warnings can be ignored, especially from --strict run, but the code here
> looks like it needs a fix. Feel free to get in touch if the warning is not clear.
>
>
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   interrupt-parent = <&gic>;
> > +
> > +   aliases {
> > +           serial12 = &uart12;
>
> Nope. Such aliases are board specific.
Agree, I will move to ast2700-evb.dts.

>
> > +   };
> > +
> > +   cpus {
> > +           #address-cells = <1>;
> > +           #size-cells = <0>;
> > +
> > +           cpu@0 {
> > +                   compatible = "arm,cortex-a35";
> > +                   enable-method = "psci";
> > +                   device_type = "cpu";
> > +                   reg = <0>;
> > +                   d-cache-size = <0x8000>;
> > +                   d-cache-line-size = <64>;
> > +                   d-cache-sets = <128>;
> > +                   i-cache-size = <0x8000>;
> > +                   i-cache-line-size = <64>;
> > +                   i-cache-sets = <256>;
> > +                   next-level-cache = <&l2>;
> > +           };
> > +
> > +           cpu@1 {
> > +                   compatible = "arm,cortex-a35";
> > +                   enable-method = "psci";
> > +                   device_type = "cpu";
> > +                   reg = <1>;
> > +                   d-cache-size = <0x8000>;
> > +                   d-cache-line-size = <64>;
> > +                   d-cache-sets = <128>;
> > +                   i-cache-size = <0x8000>;
> > +                   i-cache-line-size = <64>;
> > +                   i-cache-sets = <256>;
> > +                   next-level-cache = <&l2>;
> > +           };
> > +
> > +           cpu@2 {
> > +                   compatible = "arm,cortex-a35";
> > +                   enable-method = "psci";
> > +                   device_type = "cpu";
> > +                   reg = <2>;
> > +                   d-cache-size = <0x8000>;
> > +                   d-cache-line-size = <64>;
> > +                   d-cache-sets = <128>;
> > +                   i-cache-size = <0x8000>;
> > +                   i-cache-line-size = <64>;
> > +                   i-cache-sets = <256>;
> > +                   next-level-cache = <&l2>;
> > +           };
> > +
> > +           cpu@3 {
> > +                   compatible = "arm,cortex-a35";
> > +                   enable-method = "psci";
> > +                   device_type = "cpu";
> > +                   reg = <3>;
> > +                   d-cache-size = <0x8000>;
> > +                   d-cache-line-size = <64>;
> > +                   d-cache-sets = <128>;
> > +                   i-cache-size = <0x8000>;
> > +                   i-cache-line-size = <64>;
> > +                   i-cache-sets = <256>;
> > +                   next-level-cache = <&l2>;
> > +           };
> > +
> > +           l2: l2-cache0 {
> > +                   compatible = "cache";
> > +                   cache-size = <0x80000>;
> > +                   cache-line-size = <64>;
> > +                   cache-sets = <1024>;
> > +                   cache-level = <2>;
> > +           };
> > +   };
> > +
> > +   pmu {
> > +           compatible = "arm,cortex-a35-pmu";
> > +           interrupt-parent = <&gic>;
> > +           interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > +   };
> > +
> > +   psci {
>
> Order the nodes according to DTS coding style.
>
> Fix all your patches:
> 1. To pass flawlessly checkpatch (you did not run it) 2. To pass
> dt_binding_check and dtbs_check (you did not run these) 3. To adhere to
> kernel coding style 4. To adhere to DTS coding style
Agree.

>
> > +           compatible = "arm,psci-1.0";
> > +           method = "smc";
> > +   };
> > +
> > +   gic: interrupt-controller@12200000 {
>
> Nope, this cannot be outside of SoC.
Agree.

>
> > +           compatible = "arm,gic-v3";
> > +           interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > +           #interrupt-cells = <3>;
> > +           interrupt-controller;
> > +           interrupt-parent = <&gic>;
> > +           #redistributor-regions = <1>;
> > +           reg =   <0 0x12200000 0 0x10000>,               //GICD
> > +                   <0 0x12280000 0 0x80000>,               //GICR
> > +                   <0 0x40440000 0 0x1000>;                //GICC
>
> Read DTS coding style and order this correctly.
Agree.

>
> > +   };
> > +
> > +   timer {
> > +           compatible = "arm,armv8-timer";
> > +           interrupt-parent = <&gic>;
> > +           interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +                           <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +                           <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +                           <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +           arm,cpu-registers-not-fw-configured;
> > +           always-on;
> > +   };
> > +
> > +   soc0: soc@10000000 {
> > +           compatible = "simple-bus";
> > +           #address-cells = <2>;
> > +           #size-cells = <2>;
> > +           ranges;
> > +
> > +           soc0_sram: sram@10000000 {
> > +                   compatible = "mmio-sram";
> > +                   reg = <0x0 0x10000000 0x0 0x20000>;     /* 128KiB SRAM on soc0
> */
> > +                   ranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>;
> > +                   #address-cells = <2>;
> > +                   #size-cells = <2>;
> > +                   no-memory-wc;
> > +
> > +                   exported@0 {
> > +                           reg = <0 0x0 0 0x20000>;
> > +                           export;
> > +                   };
> > +           };
> > +
> > +           syscon0: syscon@12c02000 {
> > +                   compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
> > +                   reg = <0x0 0x12c02000 0x0 0x1000>;
> > +                   ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
> > +                   #address-cells = <2>;
> > +                   #size-cells = <2>;
> > +                   #clock-cells = <1>;
> > +                   #reset-cells = <1>;
> > +
> > +                   silicon-id@0 {
> > +                           compatible = "aspeed,ast2700-silicon-id",
> "aspeed,silicon-id";
> > +                           reg = <0 0x0 0 0x4>;
> > +                   };
> > +
> > +                   scu_ic0: interrupt-controller@1D0 {
>
> DTS coding style...
Agree. I will fix to "scu_ic0: interrupt-controller@1d0 {"

>
> > +                           #interrupt-cells = <1>;
> > +                           compatible = "aspeed,ast2700-scu-ic0";
> > +                           reg = <0 0x1d0 0 0xc>;
> > +                           interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> > +                           interrupt-controller;
> > +                   };
> > +
> > +                   scu_ic1: interrupt-controller@1E0 {
> > +                           #interrupt-cells = <1>;
> > +                           compatible = "aspeed,ast2700-scu-ic1";
> > +                           reg = <0 0x1e0 0 0xc>;
> > +                           interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> > +                           interrupt-controller;
> > +                   };
> > +
> > +                   soc0_rst: reset-controller@200 {
> > +                           reg = <0 0x200 0 0x40>;
> > +                   };
> > +
> > +                   soc0_clk: clock-controller@240 {
> > +                           reg = <0 0x240 0 0x1c0>;
> > +                   };
> > +           };
> > +
> > +   };
> > +
> > +   soc1: soc@14000000 {
>
> Wait, what, to socs?
Yes.
In AST2700, there are two socs with different base address for use.

>
> > +           compatible = "simple-bus";
> > +           #address-cells = <2>;
> > +           #size-cells = <2>;
> > +           ranges;
> > +
> > +           syscon1: syscon@14c02000 {
> > +                   compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
> > +                   reg = <0x0 0x14c02000 0x0 0x1000>;
> > +                   ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
> > +                   #address-cells = <2>;
> > +                   #size-cells = <2>;
> > +                   #clock-cells = <1>;
> > +                   #reset-cells = <1>;
> > +
> > +                   soc1_rst: reset-controller@200 {
> > +                           #reset-cells = <1>;
> > +                   };
> > +
> > +                   soc1_clk: clock-controller@240 {
> > +                           reg = <0 0x240 0 0x1c0>;
> > +                   };
> > +           };
> > +
> > +           uart12: serial@14c33b00 {
> > +                   compatible = "ns16550a";
> > +                   reg = <0x0 0x14c33b00 0x0 0x100>;
> > +                   reg-shift = <2>;
> > +                   reg-io-width = <4>;
> > +                   clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
> > +                   no-loopback-test;
> > +                   pinctrl-names = "default";
>
> What is this?
BMC UART is used in uart12 in soc1.

>
> > +           };
> > +   };
> > +};
> > +
>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 04/10] dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset

[Kevin Chen]

Hi Krzk,

I will separate clock part in the v3 patch into Ryan's clock series.
> > ---
>
> Sorry, that's not acceptable. This does not have even SoB.
Agree.

>
> All previous comments apply.
Agree.

>
> Best regards,
> Krzysztof

--
Best Regards,
Kevin.Chen
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RE: [PATCH v1 05/10] dt-bindings: arm: aspeed: Add maintainer

[Kevin Chen]

Hi Krzk,

>
> Why?
Agree, I will remove it.

>
> > ---
> >  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> Best regards,
> Krzysztof

--
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Kevin.Chen
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RE: [PATCH v1 07/10] arm64: aspeed: Add support for ASPEED AST2700 BMC SoC

[Kevin Chen]

Hi Krzk,

> > ---
> >  MAINTAINERS                  |  3 +++
> >  arch/arm64/Kconfig.platforms | 14 ++++++++++++++
> >  2 files changed, 17 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > c0a3d9e93689..08609430cfe0 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -2121,7 +2121,10 @@ Q:
>       https://patchwork.ozlabs.org/project/linux-aspeed/list/
> >  T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git
> >  F: Documentation/devicetree/bindings/arm/aspeed/
> >  F: arch/arm/boot/dts/aspeed/
> > +F: arch/arm64/boot/dts/aspeed/
> >  F: arch/arm/mach-aspeed/
> > +F: include/dt-bindings/clock/aspeed,ast2700-clk.h
> > +F: include/dt-bindings/reset/aspeed,ast2700-reset.h
> >  N: aspeed
> >
> >  ARM/AXM LSI SOC
> > diff --git a/arch/arm64/Kconfig.platforms
> > b/arch/arm64/Kconfig.platforms index 6c6d11536b42..1db7b6f1ee0a 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -40,6 +40,20 @@ config ARCH_APPLE
> >       This enables support for Apple's in-house ARM SoC family, starting
> >       with the Apple M1.
> >
> > +config ARCH_ASPEED
> > +   bool "Aspeed SoC family"
> > +   select MACH_ASPEED_G7
> > +   help
> > +     Say yes if you intend to run on an Aspeed ast2700 or similar
> > +     seventh generation Aspeed BMCs.
> > +
> > +config MACH_ASPEED_G7
> > +   bool "Aspeed SoC AST2700"
>
> There are no MACHines for arm64. Look at this code. Do you see MACH
> anywhere else? No. Then why Aspeed must be different?
>
> No. Drop.
Agree.

>
> Best regards,
> Krzysztof

--
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Kevin.Chen
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RE: [PATCH v1 06/10] dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string

[Kevin Chen]

Hi Krzk,

> > ---
> >  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> > b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> > index 71c31c08a8ad..b21551817f44 100644
> > --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> > +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> > @@ -99,4 +99,9 @@ properties:
> >                - ufispace,ncplite-bmc
> >            - const: aspeed,ast2600
> >
> > +      - description: AST2700 based boards
> > +        items:
> > +          - enum:
> > +              - aspeed,ast2700-evb
>
> NAK, this cannot be alone. Look at all other examples. Why are you doing
> things differently?
Disagree, ast2700-evb is 7th generation IC in ASPEED.
It not in the sub-set of AST2400/AST2500/AST2600 based boards.

>
> Best regards,
> Krzysztof

--
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Kevin.Chen
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Re: 回覆: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree

[Krzysztof Kozlowski]

On 15/08/2024 07:50, Kevin Chen wrote:
>>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>> new file mode 100644
>>> index 000000000000..858ab95251e4
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>> @@ -0,0 +1,217 @@
>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>> +#include <dt-bindings/clock/aspeed,ast2700-clk.h>
>>> +#include <dt-bindings/reset/aspeed,ast2700-reset.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
>>> +
>>> +/ {
>>> +     model = "Aspeed BMC";
>>
>> Model of what? No, drop.
> Can I change to "model = "AST2700 EVB""

Model of what? No, it does not make sense here.


..


>>> +
>>> +             uart12: serial@14c33b00 {
>>> +                     compatible = "ns16550a";
>>> +                     reg = <0x0 0x14c33b00 0x0 0x100>;
>>> +                     reg-shift = <2>;
>>> +                     reg-io-width = <4>;
>>> +                     clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
>>> +                     no-loopback-test;
>>> +                     pinctrl-names = "default";
>>
>> What is this?
> BMC uart using in uart12 in soc1.

No, that line. pinctrl-names do not make sense here without values.

> 
>>
>>> +             };
>>> +     };
>>> +};
>>> +
> 
> --
> Best Regards,
> Kevin. Chen
> ________________________________
> 寄件者: Krzysztof Kozlowski <krzk@kernel.org>
> 寄件日期: 2024年7月26日 下午 07:19
> 收件者: Kevin Chen <kevin_chen@aspeedtech.com>; robh@kernel.org <robh@kernel.org>; krzk+dt@kernel.org <krzk+dt@kernel.org>; conor+dt@kernel.org <conor+dt@kernel.org>; joel@jms.id.au <joel@jms.id.au>; andrew@codeconstruct.com.au <andrew@codeconstruct.com.au>; lee@kernel.org <lee@kernel.org>; catalin.marinas@arm.com <catalin.marinas@arm.com>; will@kernel.org <will@kernel.org>; arnd@arndb.de <arnd@arndb.de>; olof@lixom.net <olof@lixom.net>; soc@kernel.org <soc@kernel.org>; mturquette@baylibre.com <mturquette@baylibre.com>; sboyd@kernel.org <sboyd@kernel.org>; p.zabel@pengutronix.de <p.zabel@pengutronix.de>; quic_bjorande@quicinc.com <quic_bjorande@quicinc.com>; geert+renesas@glider.be <geert+renesas@glider.be>; dmitry.baryshkov@linaro.org <dmitry.baryshkov@linaro.org>; shawnguo@kernel.org <shawnguo@kernel.org>; neil.armstrong@linaro.org <neil.armstrong@linaro.org>; m.szyprowski@samsung.com <m.szyprowski@samsung.com>; nfraprado@collabora.com <nfraprado@collabora.com>; u-kumar1@ti.com <u-kumar1@ti.com>; devicetree@vger.kernel.org <devicetree@vger.kernel.org>; linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>; linux-aspeed@lists.ozlabs.org <linux-aspeed@lists.ozlabs.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>
> 主旨: Re: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree
> 

Why do you quote my email twice?


...

>> +             uart12: serial@14c33b00 {
>> +                     compatible = "ns16550a";
>> +                     reg = <0x0 0x14c33b00 0x0 0x100>;
>> +                     reg-shift = <2>;
>> +                     reg-io-width = <4>;
>> +                     clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
>> +                     no-loopback-test;
>> +                     pinctrl-names = "default";
> 
> What is this?
> 
>> +             };
>> +     };
>> +};
>> +
> 
> Best regards,
> Krzysztof
> 
> ************* Email Confidentiality Notice ********************
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> 
> DISCLAIMER:
> This message (and any attachments) may contain legally privileged and/or other confidential information. If you have received it in error, please notify the sender by reply e-mail and immediately delete the e-mail and any attachments without copying or disclosing the contents. Thank you.

Maybe I am the intended recipient of your message, maybe not. I don't
want to have any legal questions regarding upstream, public
collaboration, thus probably I should just remove your messages.

Please talk with your IT that such disclaimers in open-source are not
desired (and maybe even harmful).
If you do not understand why, please also see:
https://www.youtube.com/live/fMeH7wqOwXA?si=GY7igfbda6vnjXlJ&t=835

If you need to go around company SMTP server, then consider using b4
web-relay: https://b4.docs.kernel.org/en/latest/contributor/send.html

Please be informed that by responding to this email you agree that all
communications from you and/or your company is made public. In other
words, all messages originating from you and/or your company will be
made public.

Best regards,
Krzysztof

Re: [PATCH v1 06/10] dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string

[Krzysztof Kozlowski]

On 16/08/2024 06:08, Kevin Chen wrote:
> Hi Krzk,
> 
>>> ---
>>>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++
>>>  1 file changed, 5 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>> b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>> index 71c31c08a8ad..b21551817f44 100644
>>> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>> @@ -99,4 +99,9 @@ properties:
>>>                - ufispace,ncplite-bmc
>>>            - const: aspeed,ast2600
>>>
>>> +      - description: AST2700 based boards
>>> +        items:
>>> +          - enum:
>>> +              - aspeed,ast2700-evb
>>
>> NAK, this cannot be alone. Look at all other examples. Why are you doing
>> things differently?
> Disagree, ast2700-evb is 7th generation IC in ASPEED.

I gave you argument and you just respond "disagree" with unrelated
statement?
> It not in the sub-set of AST2400/AST2500/AST2600 based boards.


? That does not answer at all my concerns. Bring me any example doing
this that way: single board compatible.

Answer to the argument, instead of bringing useless text "ast is a
board". Yeah, of course it is. What else could it be? A ship? A car?

Best regards,
Krzysztof

RE: [PATCH v1 06/10] dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string

[Kevin Chen]

> > Hi Krzk,
> >
> >>> ---
> >>>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++
> >>>  1 file changed, 5 insertions(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >>> b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >>> index 71c31c08a8ad..b21551817f44 100644
> >>> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >>> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >>> @@ -99,4 +99,9 @@ properties:
> >>>                - ufispace,ncplite-bmc
> >>>            - const: aspeed,ast2600
> >>>
> >>> +      - description: AST2700 based boards
> >>> +        items:
> >>> +          - enum:
> >>> +              - aspeed,ast2700-evb
> >>
> >> NAK, this cannot be alone. Look at all other examples. Why are you
> >> doing things differently?
> > Disagree, ast2700-evb is 7th generation IC in ASPEED.
> 
> I gave you argument and you just respond "disagree" with unrelated
> statement?
> > It not in the sub-set of AST2400/AST2500/AST2600 based boards.
> 
> 
> ? That does not answer at all my concerns. Bring me any example doing this
> that way: single board compatible.
In current stage, we only have one kind of ASPEED AST2700 evaluation board.
Should I add const for aspeed,ast2700 as the following.
      - description: AST2700 based boards 
        items: 
          - enum: 
              - aspeed,ast2700-evb 
          - const: aspeed,ast2700

> 
> Answer to the argument, instead of bringing useless text "ast is a board". Yeah,
> of course it is. What else could it be? A ship? A car?

> 
> Best regards,
> Krzysztof

RE: 回覆: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree

[Kevin Chen]

> >>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>> new file mode 100644
> >>> index 000000000000..858ab95251e4
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>> @@ -0,0 +1,217 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-or-later #include
> >>> +<dt-bindings/clock/aspeed,ast2700-clk.h>
> >>> +#include <dt-bindings/reset/aspeed,ast2700-reset.h>
> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >>> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> >>> +
> >>> +/ {
> >>> +     model = "Aspeed BMC";
> >>
> >> Model of what? No, drop.
> > Can I change to "model = "AST2700 EVB""
> 
> Model of what? No, it does not make sense here.
Should I change to model = "Aspeed BMC SoC";

> 
> 
> ..
> 
> 
> >>> +
> >>> +             uart12: serial@14c33b00 {
> >>> +                     compatible = "ns16550a";
> >>> +                     reg = <0x0 0x14c33b00 0x0 0x100>;
> >>> +                     reg-shift = <2>;
> >>> +                     reg-io-width = <4>;
> >>> +                     clocks = <&syscon1
> SCU1_CLK_GATE_UART12CLK>;
> >>> +                     no-loopback-test;
> >>> +                     pinctrl-names = "default";
> >>
> >> What is this?
> > BMC uart using in uart12 in soc1.
> 
> No, that line. pinctrl-names do not make sense here without values.
Agree, I will remove the line of pinctrl-names in next patch.
Pinctrl property needed to be defined in the future patches.

> 
> >
> >>
> >>> +             };
> >>> +     };
> >>> +};
> >>> +
> >
> > --
> > Best Regards,
> > Kevin. Chen
> >
> 
> Why do you quote my email twice?
> 
> 
> ...
> 
> >> +             uart12: serial@14c33b00 {
> >> +                     compatible = "ns16550a";
> >> +                     reg = <0x0 0x14c33b00 0x0 0x100>;
> >> +                     reg-shift = <2>;
> >> +                     reg-io-width = <4>;
> >> +                     clocks = <&syscon1
> SCU1_CLK_GATE_UART12CLK>;
> >> +                     no-loopback-test;
> >> +                     pinctrl-names = "default";
> >
> > What is this?
> >
> >> +             };
> >> +     };
> >> +};
> >> +
> >
> > Best regards,
> > Krzysztof
> >
> other confidential information. If you have received it in error, please notify the
> sender by reply e-mail and immediately delete the e-mail and any
> attachments without copying or disclosing the contents. Thank you.
> 
> Maybe I am the intended recipient of your message, maybe not. I don't want to
> have any legal questions regarding upstream, public collaboration, thus
> probably I should just remove your messages.
> 
> Please talk with your IT that such disclaimers in open-source are not desired
> (and maybe even harmful).
> If you do not understand why, please also see:
> https://www.youtube.com/live/fMeH7wqOwXA?si=GY7igfbda6vnjXlJ&t=835
> 
> If you need to go around company SMTP server, then consider using b4
> web-relay: https://b4.docs.kernel.org/en/latest/contributor/send.html
> 
> Please be informed that by responding to this email you agree that all
> communications from you and/or your company is made public. In other words,
> all messages originating from you and/or your company will be made public.
> 
> Best regards,
> Krzysztof

Re: 回覆: [PATCH v1 01/10] dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU

[Krzysztof Kozlowski]

On 15/08/2024 07:50, Kevin Chen wrote:
> Hi Krzk,
> 
> I will speperate clock part in the v3 patch into Ryan's clock series.
> 
>> Missing commit msg.
>>
>> Please use subject prefixes matching the subsystem. You can get them for
>> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
>> your patch is touching. For bindings, the preferred subjects are
>> explained here:
>> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>>
>> A nit, subject: drop second/last, redundant "bindings for". The
>> "dt-bindings" prefix is already stating that these are bindings.
>> See also:
>> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> Agree, already fixed in another commit in Ryan's series.
> [1/4] dt-bindings: mfd: aspeed: support fo

Just to make it clear: you responded after 2.5 months. This patchset is
neither in my mailbox nor in my brain.

Best regards,
Krzysztof

Re: 回覆: [PATCH v1 01/10] dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU

[Krzysztof Kozlowski]

On 07/10/2024 13:03, Krzysztof Kozlowski wrote:
> On 15/08/2024 07:50, Kevin Chen wrote:
>> Hi Krzk,
>>
>> I will speperate clock part in the v3 patch into Ryan's clock series.
>>
>>> Missing commit msg.
>>>
>>> Please use subject prefixes matching the subsystem. You can get them for
>>> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
>>> your patch is touching. For bindings, the preferred subjects are
>>> explained here:
>>> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>>>
>>> A nit, subject: drop second/last, redundant "bindings for". The
>>> "dt-bindings" prefix is already stating that these are bindings.
>>> See also:
>>> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
>> Agree, already fixed in another commit in Ryan's series.
>> [1/4] dt-bindings: mfd: aspeed: support fo
> 
> Just to make it clear: you responded after 2.5 months. This patchset is
> neither in my mailbox nor in my brain.

Uh, this was supposed to be replied to your recent emails.

Best regards,
Krzysztof

Re: 回覆: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree

[Krzysztof Kozlowski]

On 07/10/2024 11:26, Kevin Chen wrote:
>>>>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>> new file mode 100644
>>>>> index 000000000000..858ab95251e4
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>> @@ -0,0 +1,217 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0-or-later #include
>>>>> +<dt-bindings/clock/aspeed,ast2700-clk.h>
>>>>> +#include <dt-bindings/reset/aspeed,ast2700-reset.h>
>>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
>>>>> +
>>>>> +/ {
>>>>> +     model = "Aspeed BMC";
>>>>
>>>> Model of what? No, drop.
>>> Can I change to "model = "AST2700 EVB""
>>
>> Model of what? No, it does not make sense here.
> Should I change to model = "Aspeed BMC SoC";

SoCs do not have models. Please take a look how *every* other SoC is doing.

Best regards,
Krzysztof